From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Oct 2022 23:35:34 +0000 (+0100)
Subject: fix format in debug log
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f00dfe29126e03810f7b26aa889509a42f447e9;p=openpower-isa.git

fix format in debug log
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 35858b9d..ee345363 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2201,7 +2201,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             reg_prefix = 'r'
         # check zeroing due to predicate bit being zero
         if self.is_svp64_mode and self.pred_dst_zero:
-            log('zeroing reg %d %s' % (regnum, str(output)), is_vec)
+            log('zeroing reg %s %s' % (str(regnum), str(output)), is_vec)
             output = SelectableInt(0, 256)
         log("write reg %s%s 0x%x ew %d" % (reg_prefix, str(regnum),
                                            output.value, ew_dst),