From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Feb 2022 11:56:39 +0000 (+0000)
Subject: update README
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f03df1546c8cf6ab91ef63b04713dca768a84c4;p=libresoc-litex.git

update README
---

diff --git a/README.txt b/README.txt
index 4dd5e0d..3b73058 100644
--- a/README.txt
+++ b/README.txt
@@ -1,24 +1,37 @@
 # sim openocd test
 
 in the soc directory, create the verilog file
+
     "python issuer_verilog.py libresoc.v"
 
-copy to libresoc/ directory
-terminal 1: ./sim.py
-terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
+copy to libresoc/ directory and open a second terminal
+
+terminal 1:
+
+    ./sim.py
+
+terminal 2:
+
+    openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
 
 # ecp5 build
 
 same thing: first build libresoc.v and copy it to the libresoc/ directory
 
-./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
-./versa_ecp5.py --sys-clk-freq=55e6 --load
+    ./versa_ecp5.py --sys-clk-freq=55e6 --build --yosys-nowidelut
+    ./versa_ecp5.py --sys-clk-freq=55e6 --load
+
+ulx3s:
+
+    ./versa_ecp5.py --sys-clk-freq=12.5e6 --build --fpga=ulx3s85f \
+                    --yosys-nowidelut
+    ./versa_ecp5.py --sys-clk-freq=12.5e6 --load --fpga=ulx3s85f
 
 # arty a7 build
 
-export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
-./versa_ecp5.py --sys-clk-freq=25e6 --build  --fpga=artya7100t \
-                    --toolchain=symbiflow
-./versa_ecp5.py --sys-clk-freq=25e6 --load --fpga=artya7100t  \
-                    --toolchain=symbiflow
+    export PATH=$PATH:/usr/local/symbiflow/bin/:/usr/local/symbiflow/vtr/bin/
+    ./versa_ecp5.py --sys-clk-freq=25e6 --build  --fpga=artya7100t \
+                        --toolchain=symbiflow
+    ./versa_ecp5.py --sys-clk-freq=25e6 --load --fpga=artya7100t  \
+                        --toolchain=symbiflow