From: Jakub Jelinek <jakub@redhat.com>
Date: Tue, 15 Sep 2020 07:37:48 +0000 (+0200)
Subject: i386: Fix up vector mul and div with broadcasts in -masm=intel mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f079e104a8d1994b6b47169a6b45737615eb2d7;p=gcc.git

i386: Fix up vector mul and div with broadcasts in -masm=intel mode

These patterns printed bogus <>s around the {1to16} and similar strings.

2020-09-15  Jakub Jelinek  <jakub@redhat.com>

	PR target/97028
	* config/i386/sse.md (mul<mode>3<mask_name>_bcs,
	<avx512>_div<mode>3<mask_name>_bcst): Use <avx512bcst> instead of
	<<avx512bcst>>.

	* gcc.target/i386/avx512f-pr97028.c: Untested fix.
---

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a784346a23b..934b60a288f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1867,7 +1867,7 @@
 	     (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
 	  (match_operand:VF_AVX512 2 "register_operand" "v")))]
   "TARGET_AVX512F && <mask_mode512bit_condition>"
-  "vmul<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<<avx512bcst>>}"
+  "vmul<ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<avx512bcst>}"
   [(set_attr "prefix" "evex")
    (set_attr "type" "ssemul")
    (set_attr "mode" "<MODE>")])
@@ -1960,7 +1960,7 @@
 	  (vec_duplicate:VF_AVX512
 	     (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
   "TARGET_AVX512F && <mask_mode512bit_condition>"
-  "vdiv<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<<avx512bcst>>}"
+  "vdiv<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<avx512bcst>}"
   [(set_attr "prefix" "evex")
     (set_attr "type" "ssediv")
    (set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr97028.c b/gcc/testsuite/gcc.target/i386/avx512f-pr97028.c
new file mode 100644
index 00000000000..2719108a411
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-pr97028.c
@@ -0,0 +1,18 @@
+/* PR target/97028 */
+/* { dg-do assemble { target avx512f } } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-O2 -mavx512f -masm=intel" } */
+
+#include <x86intrin.h>
+
+__m512
+foo (__m512 x, float *y)
+{
+  return _mm512_mul_ps (x, _mm512_set1_ps (*y));
+}
+
+__m512
+bar (__m512 x, float *y)
+{
+  return _mm512_div_ps (x, _mm512_set1_ps (*y));
+}