From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 15 Jul 2020 15:07:12 +0000 (+0200)
Subject: Add early code for RAM calibration
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f57cdc017ddf4050a21dab8bfaf2c0fe70c2219;p=gram.git

Add early code for RAM calibration
---

diff --git a/libgram/Makefile b/libgram/Makefile
index e1131df..fffed37 100644
--- a/libgram/Makefile
+++ b/libgram/Makefile
@@ -1,4 +1,4 @@
-OBJS := src/init.o src/memtest.o src/dfii.o
+OBJS := src/init.o src/memtest.o src/dfii.o src/calibration.o
 
 TRIPLE := riscv64-unknown-elf-
 
diff --git a/libgram/include/gram.h b/libgram/include/gram.h
index 413af3a..aa1d9c0 100644
--- a/libgram/include/gram.h
+++ b/libgram/include/gram.h
@@ -26,6 +26,7 @@ struct gramCtx {
 
 extern __attribute__((visibility ("default"))) int gram_init(struct gramCtx *ctx, void *ddr_base, void *core_base, void *phy_base);
 extern __attribute__((visibility ("default"))) int gram_memtest(struct gramCtx *ctx, size_t length, enum GramWidth width);
+extern __attribute__((visibility ("default"))) int gram_calibration_auto(struct gramCtx *ctx);
 
 #ifdef GRAM_RW_FUNC
 extern uint32_t gram_read(struct gramCtx *ctx, void *addr);
diff --git a/libgram/src/calibration.c b/libgram/src/calibration.c
new file mode 100644
index 0000000..1d29e47
--- /dev/null
+++ b/libgram/src/calibration.c
@@ -0,0 +1,77 @@
+#include <stdint.h>
+
+#include "hw_regs.h"
+#include <gram.h>
+#include "dfii.h"
+#include "helpers.h"
+
+static void set_dly_sel(struct gramCtx *ctx, int sel) {
+#ifdef GRAM_RW_FUNC
+	gram_write(ctx, &(ctx->phy->dly_sel), sel);
+#else
+	ctx->phy->dly_sel = sel;
+#endif
+}
+
+static void rdly_dq_inc(struct gramCtx *ctx) {
+#ifdef GRAM_RW_FUNC
+	gram_write(ctx, &(ctx->phy->rdly_dq_inc), 1);
+#else
+	ctx->phy->rdly_dq_inc = 1;
+#endif
+}
+
+static void rdly_dq_bitslip_inc(struct gramCtx *ctx) {
+#ifdef GRAM_RW_FUNC
+	gram_write(ctx, &(ctx->phy->rdly_dq_bitslip), 1);
+#else
+	ctx->phy->rdly_dq_bitslip = 1;
+#endif
+}
+
+static void read_delay_inc(struct gramCtx *ctx, int module) {
+	/* sel module */
+	set_dly_sel(ctx, 1 << module);
+
+	/* inc delay */
+	rdly_dq_inc(ctx);
+
+	/* unsel module */
+	set_dly_sel(ctx, 0);
+
+	/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
+	set_dly_sel(ctx, 0xFF);
+	set_dly_sel(ctx, 0);
+}
+
+static void bitslip_inc(struct gramCtx *ctx, int module) {
+	/* sel module */
+	set_dly_sel(ctx, 1 << module);
+
+	/* inc delay */
+	rdly_dq_bitslip_inc(ctx);
+
+	/* unsel module */
+	set_dly_sel(ctx, 0);
+
+	/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
+	set_dly_sel(ctx, 0xFF);
+	set_dly_sel(ctx, 0);
+}
+
+int gram_calibration_auto(struct gramCtx *ctx) {
+	dfii_setsw(ctx, true);
+
+	// TODO: reset all delays and bitslip
+
+	read_delay_inc(ctx, 0);
+	read_delay_inc(ctx, 1);
+
+	dfii_setsw(ctx, false);
+
+	return 0;
+}
+
+void gram_load_calibration(void) {
+
+}