From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 23 Nov 2012 18:17:49 +0000 (+0100)
Subject: fhdl/structure: add Memory.get_port API
X-Git-Tag: 24jan2021_ls180~2099^2~761
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f6215a13a69c2209fe62d615df585ae8d67fb72;p=litex.git

fhdl/structure: add Memory.get_port API
---

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 19cafefc..04a5b13c 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -308,6 +308,7 @@ class Instance(HUID):
 
 (READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
 
+# NOTE: Direct use of MemoryPort is deprecated. Use Memory.get_port() instead.
 class MemoryPort:
 	def __init__(self, adr, dat_r, we=None, dat_w=None,
 	  async_read=False, re=None, we_granularity=0, mode=WRITE_FIRST,
@@ -322,13 +323,35 @@ class MemoryPort:
 		self.mode = mode
 		self.clock_domain = clock_domain
 
+# NOTE: ports parameter will be removed
 class Memory(HUID):
 	def __init__(self, width, depth, *ports, init=None):
 		super().__init__()
 		self.width = width
 		self.depth = depth
-		self.ports = ports
+		self.ports = list(ports)
 		self.init = init
+	
+	def get_port(self, write_capable=False, async_read=False,
+	  has_re=False, we_granularity=0, mode=WRITE_FIRST,
+	  clock_domain="sys"):
+		adr = Signal(BV(bits_for(self.depth-1)))
+		dat_r = Signal(BV(self.width))
+		if write_capable:
+			we = Signal()
+			dat_w = Signal(BV(self.width))
+		else:
+			we = None
+			dat_w = None
+		if has_re:
+			re = Signal()
+		else:
+			re = None
+		mp = MemoryPort(adr, dat_r, we, dat_w,
+		async_read, re, we_granularity, mode,
+		clock_domain)
+		self.ports.append(mp)
+		return mp
 
 #