From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 14:54:09 +0000 (+0000)
Subject: multi-out temporary, simplify graphs
X-Git-Tag: ls180-24jan2020~1421
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f6bbbccf3e0b5c0809dd35173fa83c7600571e4;p=ieee754fpu.git

multi-out temporary, simplify graphs
---

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index 5ebdd664..b1562a06 100644
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -191,7 +191,9 @@ class CombMultiOutPipeline(MultiOutControlBase):
 
         # temporaries
         p_i_valid = Signal(reset_less=True)
+        pv = Signal(reset_less=True)
         m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
+        m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
 
         # all outputs to next stages first initialised to zero (invalid)
         # the only output "active" is then selected by the muxid
@@ -201,7 +203,7 @@ class CombMultiOutPipeline(MultiOutControlBase):
         m.d.comb += self.p.o_ready.eq(~data_valid | self.n[mid].i_ready)
         m.d.comb += data_valid.eq(p_i_valid | \
                                     (~self.n[mid].i_ready & data_valid))
-        with m.If(self.p.i_valid & self.p.o_ready):
+        with m.If(pv):
             m.d.comb += eq(r_data, self.p.i_data)
         m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))