From: lkcl <lkcl@web>
Date: Fri, 13 Nov 2020 02:07:06 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1839
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f7fd61c7143e74237c158b33b964aae911b5a9c;p=libreriscv.git

---

diff --git a/openpower/sv/major_opcode_allocation.mdwn b/openpower/sv/major_opcode_allocation.mdwn
index 3c551fd9f..2dc253b8c 100644
--- a/openpower/sv/major_opcode_allocation.mdwn
+++ b/openpower/sv/major_opcode_allocation.mdwn
@@ -51,10 +51,9 @@ Potential ways to reduce pressure on the 16 bit space are:
 
 This latter would be useful in the Vector context to have an alternative meaning: as the bit which determines whether the instruction is 11-bit prefixed or 27-bit prefixed:
 
-'''
-0 1 2 3 4 5 6 7 8 9 a b c d e f |
-|major op | 11 bit vector prefix|
-|16 bit opcode  alt vec. mode ^ |
-| extra vector prefix if alt set|
-'''
+    0 1 2 3 4 5 6 7 8 9 a b c d e f |
+    |major op | 11 bit vector prefix|
+    |16 bit opcode  alt vec. mode ^ |
+    | extra vector prefix if alt set|
+