From: Wesley W. Terpstra <wesley@sifive.com>
Date: Sun, 14 May 2017 06:38:20 +0000 (-0700)
Subject: uart: power-on with the right divider for the design (#15)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f8722f80c16a649882d02f03d000da946eee737;p=sifive-blocks.git

uart: power-on with the right divider for the design (#15)
---

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 9b3dfaa..e6349f1 100644
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -203,7 +203,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
   val rxm = Module(new UARTRx(params))
   val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
 
-  val divinit = 542 // (62.5MHz / 115200)
+  val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200
   val div = Reg(init = UInt(divinit, uartDivisorBits))
 
   private val stopCountBits = log2Up(uartStopBits)