From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Sun, 24 May 2020 14:44:32 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f9d008a15c8b02882003be602b56e7b01beb357;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
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diff --git a/39/0b9524242ccec40fe44231a14db483896faabe b/39/0b9524242ccec40fe44231a14db483896faabe
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+Date: Sun, 24 May 2020 14:44:32 +0000
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+Message-ID: <bug-336-13-1LcdVrfoWU@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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