From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 5 Mar 2020 18:35:55 +0000 (+0000)
Subject: add "form" to power decode
X-Git-Tag: div_pipeline~1775
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0f9f9d87026263481e96344ad7cf5ecf75f7d445;p=soc.git

add "form" to power decode
---

diff --git a/src/decoder/power_decoder.py b/src/decoder/power_decoder.py
index 1b15e952..6176e496 100644
--- a/src/decoder/power_decoder.py
+++ b/src/decoder/power_decoder.py
@@ -55,7 +55,7 @@ Top Level:
 
 from nmigen import Module, Elaboratable, Signal
 from nmigen.cli import rtlil
-from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
+from power_enums import (Function, Form, InternalOp, In1Sel, In2Sel, In3Sel,
                          OutSel, RC, LdstLen, CryIn, get_csv, single_bit_flags,
                          get_signal_name, default_values)
 from collections import namedtuple
@@ -71,6 +71,7 @@ class PowerOp:
     def __init__(self):
         self.function_unit = Signal(Function, reset_less=True)
         self.internal_op = Signal(InternalOp, reset_less=True)
+        self.form = Signal(form, reset_less=True)
         self.in1_sel = Signal(In1Sel, reset_less=True)
         self.in2_sel = Signal(In2Sel, reset_less=True)
         self.in3_sel = Signal(In3Sel, reset_less=True)
@@ -86,6 +87,7 @@ class PowerOp:
         if row is None:
             row = default_values
         res = [self.function_unit.eq(Function[row['unit']]),
+               self.form.eq(Form[row['form']]),
                self.internal_op.eq(InternalOp[row['internal op']]),
                self.in1_sel.eq(In1Sel[row['in1']]),
                self.in2_sel.eq(In2Sel[row['in2']]),
@@ -102,6 +104,7 @@ class PowerOp:
 
     def eq(self, otherop):
         res = [self.function_unit.eq(otherop.function_unit),
+               self.form.eq(otherop.form),
                self.internal_op.eq(otherop.internal_op),
                self.in1_sel.eq(otherop.in1_sel),
                self.in2_sel.eq(otherop.in2_sel),
@@ -123,7 +126,8 @@ class PowerOp:
                    self.out_sel,
                    self.ldst_len,
                    self.rc_sel,
-                   self.internal_op]
+                   self.internal_op,
+                   self.form]
         single_bit_ports = [getattr(self, get_signal_name(x))
                             for x in single_bit_flags]
         return regular + single_bit_ports
diff --git a/src/decoder/power_enums.py b/src/decoder/power_enums.py
index b92c6224..8097a0eb 100644
--- a/src/decoder/power_enums.py
+++ b/src/decoder/power_enums.py
@@ -26,7 +26,7 @@ single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
                    'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
                    'ldst len': 'NONE',
-                   'rc' : 'NONE', 'cry in' : 'ZERO'}
+                   'rc' : 'NONE', 'cry in' : 'ZERO', 'form': 'NONE'}
 
 def get_signal_name(name):
     return name.lower().replace(' ', '_')
@@ -39,6 +39,39 @@ class Function(Enum):
     LDST = 2
 
 
+@unique
+class Form(Enum):
+    NONE = 0
+    I = 1
+    B = 2
+    SC = 3
+    D = 4
+    DS = 5
+    DQ = 6
+    X = 7
+    XL = 8
+    XFX = 10
+    XFL = 11
+    XX1 = 12
+    XX2 = 13
+    XX3 = 13
+    XX4 = 14
+    XS = 15
+    XO = 16
+    A = 17
+    M = 18
+    MD = 19
+    MDS = 20
+    VA = 21
+    VC = 22
+    VX = 23
+    EVX = 24
+    EVS = 25
+    Z22 = 26
+    Z23 = 27
+
+
+
 @unique
 class InternalOp(Enum):
     OP_ILLEGAL = 0