From: Luke Kenneth Casson Leighton Date: Sat, 20 Feb 2021 23:32:50 +0000 (+0000) Subject: add in Vectorised CRs when Rc=1 into ISACaller X-Git-Tag: convert-csv-opcode-to-binary~187 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0fa0da7ccac38dca3c3bfe0d4ab4e15a27367ef2;p=soc.git add in Vectorised CRs when Rc=1 into ISACaller --- diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 4a4935f2..d5399cb9 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -371,6 +371,7 @@ def get_pdecode_cr_out(dec2, name): out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data sv_cr_out = yield op.sv_cr_out spec = yield dec2.crout_svdec.spec + sv_override = yield dec2.dec_cr_out.sv_override # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec) out = yield dec2.e.write_cr.data o_isvec = yield dec2.o_isvec @@ -378,6 +379,7 @@ def get_pdecode_cr_out(dec2, name): print (" sv_cr_out", sv_cr_out) print (" cr_bf", out_bitfield) print (" spec", spec) + print (" override", sv_override) # identify which regnames map to out / o2 if name == 'CR0': if out_sel == CROutSel.CR0.value: @@ -989,7 +991,6 @@ class ISACaller: rc_en = False if rc_en: regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0") - regnum = 0 # TODO fix self.handle_comparison(results, regnum) # svp64 loop can end early if the dest is scalar diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py index a5e93e47..27a21526 100644 --- a/src/soc/decoder/isa/test_caller_svp64.py +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -123,8 +123,8 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl[0:7] = 1 # VL - svstate.maxvl[0:7] = 1 # MAXVL + svstate.vl[0:7] = 2 # VL + svstate.maxvl[0:7] = 2 # MAXVL print ("SVSTATE", bin(svstate.spr.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -133,12 +133,14 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) - print ("CR0", sim.crl[0].get_range().value) - print ("CR1", sim.crl[1].get_range().value) + # XXX TODO, these need to move to higher range (offset) + CR0 = sim.crl[0].get_range().value + CR1 = sim.crl[1].get_range().value + print ("CR0", CR0) + print ("CR1", CR1) self._check_regs(sim, expected_regs) - self.assertEqual(sim.crl[0].get_range().value, - SelectableInt(4, 4)) - + self.assertEqual(CR0, SelectableInt(2, 4)) + self.assertEqual(CR1, SelectableInt(4, 4)) def run_tst_program(self, prog, initial_regs=[0] * 32, svstate=None): diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 05914987..e3b6175d 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -660,6 +660,7 @@ class DecodeCRIn(Elaboratable): self.cr_bitfield_b = Data(3, "cr_bitfield_b") self.cr_bitfield_o = Data(3, "cr_bitfield_o") self.whole_reg = Data(8, "cr_fxm") + self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec def elaborate(self, platform): m = Module() @@ -673,6 +674,7 @@ class DecodeCRIn(Elaboratable): comb += self.cr_bitfield_b.ok.eq(0) comb += self.cr_bitfield_o.ok.eq(0) comb += self.whole_reg.ok.eq(0) + comb += self.sv_override.eq(0) # select the relevant CR bitfields with m.Switch(self.sel_in): @@ -681,9 +683,11 @@ class DecodeCRIn(Elaboratable): with m.Case(CRInSel.CR0): comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering) comb += self.cr_bitfield.ok.eq(1) + comb += self.sv_override.eq(1) with m.Case(CRInSel.CR1): comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering) comb += self.cr_bitfield.ok.eq(1) + comb += self.sv_override.eq(2) with m.Case(CRInSel.BI): comb += self.cr_bitfield.data.eq(self.dec.BI[2:5]) comb += self.cr_bitfield.ok.eq(1) @@ -729,6 +733,7 @@ class DecodeCROut(Elaboratable): self.insn_in = Signal(32, reset_less=True) self.cr_bitfield = Data(3, "cr_bitfield") self.whole_reg = Data(8, "cr_fxm") + self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec def elaborate(self, platform): m = Module() @@ -739,6 +744,7 @@ class DecodeCROut(Elaboratable): comb += self.cr_bitfield.ok.eq(0) comb += self.whole_reg.ok.eq(0) + comb += self.sv_override.eq(0) with m.Switch(self.sel_in): with m.Case(CROutSel.NONE): @@ -746,9 +752,11 @@ class DecodeCROut(Elaboratable): with m.Case(CROutSel.CR0): comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering) comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1 + comb += self.sv_override.eq(1) with m.Case(CROutSel.CR1): comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering) comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1 + comb += self.sv_override.eq(2) with m.Case(CROutSel.BF): comb += self.cr_bitfield.data.eq(self.dec.FormX.BF) comb += self.cr_bitfield.ok.eq(1) @@ -1180,16 +1188,24 @@ class PowerDecode2(PowerDecodeSubset): comb += e.write_fast2.eq(dec_o2.fast_out) # condition registers (CR) - for to_reg, fromreg, svdec in ( - (e.read_cr1, self.dec_cr_in.cr_bitfield, crin_svdec), - (e.read_cr2, self.dec_cr_in.cr_bitfield_b, crin_svdec_b), - (e.read_cr3, self.dec_cr_in.cr_bitfield_o, crin_svdec_o), - (e.write_cr, self.dec_cr_out.cr_bitfield, crout_svdec)): + for to_reg, cr, name, svdec in ( + (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec), + (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b), + (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o), + (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec)): + fromreg = getattr(cr, name) comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM comb += svdec.etype.eq(op.SV_Etype) # EXTRA2/3 for this insn comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA) with m.If(svdec.isvec): - comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output + # check if this is CR0 or CR1: treated differently + # (does not "listen" to EXTRA2/3 spec + with m.If(cr.sv_override == 1): # CR0 + comb += to_reg.data.eq(srcstep+0) # XXX TODO CR0 offset + with m.Elif(cr.sv_override == 2): # CR1 + comb += to_reg.data.eq(srcstep+1) # XXX TODO CR1 offset + with m.Else(): + comb += to_reg.data.eq(srcstep+svdec.cr_out) # 7-bit output with m.Else(): comb += to_reg.data.eq(svdec.cr_out) # 7-bit output comb += to_reg.ok.eq(fromreg.ok)