From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 20:08:38 +0000 (-0700)
Subject: Check that whiteboxes are synthesisable
X-Git-Tag: working-ls180~1237^2~104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0fa6a441f1a222b039975cf622ddca479a65cf24;p=yosys.git

Check that whiteboxes are synthesisable
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3f7edc627..bc722e492 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -722,7 +722,7 @@ struct XAigerWriter
 			write_h_buffer(box_list.size());
 
 			RTLIL::Module *holes_module = nullptr;
-			holes_module = module->design->addModule("\\__holes__");
+			holes_module = module->design->addModule("$__holes__");
 			log_assert(holes_module);
 
 			int port_id = 1;
@@ -822,17 +822,21 @@ struct XAigerWriter
 
 				Pass::call(holes_module->design, "flatten -wb");
 
-				// TODO: Should techmap all lib_whitebox-es once
+				// TODO: Should techmap/AIG all lib_whitebox-es once
 				Pass::call(holes_module->design, "techmap");
 				Pass::call(holes_module->design, "aigmap");
-				Pass::call(holes_module->design, "clean -purge");
+				for (auto cell : holes_module->cells())
+					if (!cell->type.in("$_NOT_", "$_AND_"))
+						log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
 
-				holes_module->design->selection_stack.pop_back();
+				Pass::call(holes_module->design, "clean -purge");
 
 				std::stringstream a_buffer;
 				XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
 				writer.write_aiger(a_buffer, false /*ascii_mode*/);
 
+				holes_module->design->selection_stack.pop_back();
+
 				f << "a";
 				std::string buffer_str = a_buffer.str();
 				int32_t buffer_size_be = to_big_endian(buffer_str.size());