From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 Nov 2020 13:35:24 +0000 (+0000)
Subject: add image links to ECP5 page
X-Git-Tag: convert-csv-opcode-to-binary~1885
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0fb85a6001a393718a01961464a70a8aa9b159c8;p=libreriscv.git

add image links to ECP5 page
---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 5ff231436..b754d902a 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -163,3 +163,10 @@ Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance?
 
 Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
 
+# VERSA ECP5 Connections
+
+[[!img 2020-11-03_13-22.png size="900x" ]] 
+
+[[!img 2020-11-03_13-25.png size="900x" ]] 
+
+[[!img versa_ecp5_x3_connector.jpg size="900x" ]]