From: Alexander Ivchenko Date: Tue, 15 Oct 2013 13:51:56 +0000 (+0000) Subject: predicates.md (register_or_constm1_operand): New. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0fe65b75fed76e8cfc029ccfeb2b5ed4a8f1a46c;p=gcc.git predicates.md (register_or_constm1_operand): New. * config/i386/predicates.md (register_or_constm1_operand): New. * config/i386/sse.md (unspec): Add UNSPEC_UNSIGNED_PCMP, UNSPEC_TESTM, UNSPEC_TESTNM, UNSPEC_VTERNLOG, UNSPEC_ALIGN, UNSPEC_CONFLICT, UNSPEC_MASKED_EQ, UNSPEC_MASKED_GT, UNSPEC_GATHER_PREFETCH, UNSPEC_SCATTER_PREFETCH (VI48_512): New. (avx512f_ucmp3): Ditto. (avx512f_vternlog): Ditto. (avx512f_align): Ditto. (3): Ditto. (avx512f_v): Ditto. (avx512f_): Ditto. (avx512f_eq3): Ditto. (avx512f_eq3_1): Ditto. (avx512f_gt3): Ditto. (avx512f_testm3): Ditto. (avx512f_testnm3): Ditto. (avx512pf_gatherpf): Ditto. (*avx512pf_gatherpf_mask): Ditto. (*avx512pf_gatherpf): Ditto. (avx512pf_scatterpf): Ditto. (*avx512pf_scatterpf_mask): Ditto. (*avx512pf_scatterpf): Ditto. (avx512f_vec_dup_gpr): Ditto. (clz2): Ditto. (conflict): Ditto. (REDUC_SMINMAX_MODE): Extened with wider modes. (reduc__): Ditto. (vlshr3): Ditto. (vashl3): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin Co-Authored-By: Sergey Lega From-SVN: r203605 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d3f63b8778..a492c8e3580 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,44 @@ +2013-10-15 Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/predicates.md (register_or_constm1_operand): New. + * config/i386/sse.md (unspec): Add UNSPEC_UNSIGNED_PCMP, UNSPEC_TESTM, + UNSPEC_TESTNM, UNSPEC_VTERNLOG, UNSPEC_ALIGN, UNSPEC_CONFLICT, + UNSPEC_MASKED_EQ, UNSPEC_MASKED_GT, UNSPEC_GATHER_PREFETCH, + UNSPEC_SCATTER_PREFETCH + (VI48_512): New. + (avx512f_ucmp3): Ditto. + (avx512f_vternlog): Ditto. + (avx512f_align): Ditto. + (3): Ditto. + (avx512f_v): Ditto. + (avx512f_): Ditto. + (avx512f_eq3): Ditto. + (avx512f_eq3_1): Ditto. + (avx512f_gt3): Ditto. + (avx512f_testm3): Ditto. + (avx512f_testnm3): Ditto. + (avx512pf_gatherpf): Ditto. + (*avx512pf_gatherpf_mask): Ditto. + (*avx512pf_gatherpf): Ditto. + (avx512pf_scatterpf): Ditto. + (*avx512pf_scatterpf_mask): Ditto. + (*avx512pf_scatterpf): Ditto. + (avx512f_vec_dup_gpr): Ditto. + (clz2): Ditto. + (conflict): Ditto. + (REDUC_SMINMAX_MODE): Extened with wider modes. + (reduc__): Ditto. + (vlshr3): Ditto. + (vashl3): Ditto. + 2013-10-15 Alexander Ivchenko Maxim Kuznetsov Sergey Lega diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 18f425c4b87..aeebb3dda5f 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1332,3 +1332,9 @@ (define_predicate "general_vector_operand" (ior (match_operand 0 "nonimmediate_operand") (match_code "const_vector"))) + +;; Return true if OP is either -1 constant or stored in register. +(define_predicate "register_or_constm1_operand" + (ior (match_operand 0 "register_operand") + (and (match_code "const_int") + (match_test "op == constm1_rtx")))) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3ead386daec..515326c94ae 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -87,7 +87,19 @@ ;; For AVX512F support UNSPEC_VPERMI2 UNSPEC_VPERMT2 + UNSPEC_UNSIGNED_PCMP + UNSPEC_TESTM + UNSPEC_TESTNM UNSPEC_SCATTER + UNSPEC_VTERNLOG + UNSPEC_ALIGN + UNSPEC_CONFLICT + UNSPEC_MASKED_EQ + UNSPEC_MASKED_GT + + ;; For AVX512PF support + UNSPEC_GATHER_PREFETCH + UNSPEC_SCATTER_PREFETCH ]) (define_c_enum "unspecv" [ @@ -364,6 +376,7 @@ (define_mode_iterator VI124_256_48_512 [V32QI V16HI V8SI (V8DI "TARGET_AVX512F") (V16SI "TARGET_AVX512F")]) (define_mode_iterator VI48_256 [V8SI V4DI]) +(define_mode_iterator VI48_512 [V16SI V8DI]) ;; Int-float size matches (define_mode_iterator VI4F_128 [V4SI V4SF]) @@ -1741,7 +1754,9 @@ [(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2") (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2") (V8SF "TARGET_AVX") (V4DF "TARGET_AVX") - (V4SF "TARGET_SSE")]) + (V4SF "TARGET_SSE") (V16SI "TARGET_AVX512F") + (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") + (V8DF "TARGET_AVX512F")]) (define_expand "reduc__" [(smaxmin:REDUC_SMINMAX_MODE @@ -1753,6 +1768,16 @@ DONE; }) +(define_expand "reduc__" + [(umaxmin:VI48_512 + (match_operand:VI48_512 0 "register_operand") + (match_operand:VI48_512 1 "register_operand"))] + "TARGET_AVX512F" +{ + ix86_expand_reduc (gen_3, operands[0], operands[1]); + DONE; +}) + (define_expand "reduc__" [(umaxmin:VI_256 (match_operand:VI_256 0 "register_operand") @@ -1877,6 +1902,20 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_insn "avx512f_ucmp3" + [(set (match_operand: 0 "register_operand" "=k") + (unspec: + [(match_operand:VI48_512 1 "register_operand" "v") + (match_operand:VI48_512 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_7_operand" "n")] + UNSPEC_UNSIGNED_PCMP))] + "TARGET_AVX512F" + "vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "ssecmp") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "_comi" [(set (reg:CCFP FLAGS_REG) (compare:CCFP @@ -5117,6 +5156,31 @@ operands[1] = adjust_address (operands[1], DFmode, INTVAL (operands[2]) * 8); }) +(define_insn "avx512f_vternlog" + [(set (match_operand:VI48_512 0 "register_operand" "=v") + (unspec:VI48_512 + [(match_operand:VI48_512 1 "register_operand" "0") + (match_operand:VI48_512 2 "register_operand" "v") + (match_operand:VI48_512 3 "nonimmediate_operand" "vm") + (match_operand:SI 4 "const_0_to_255_operand")] + UNSPEC_VTERNLOG))] + "TARGET_AVX512F" + "vpternlog\t{%4, %3, %2, %0|%0, %2, %3, %4}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512f_align" + [(set (match_operand:VI48_512 0 "register_operand" "=v") + (unspec:VI48_512 [(match_operand:VI48_512 1 "register_operand" "v") + (match_operand:VI48_512 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand")] + UNSPEC_ALIGN))] + "TARGET_AVX512F" + "valign\t{%3, %2, %1, %0|%0, %1, %2, %3}"; + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "avx512f_rndscale" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 @@ -6141,6 +6205,22 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) +(define_insn "3" + [(set (match_operand:VI48_512 0 "register_operand" "=v,v") + (any_lshift:VI48_512 + (match_operand:VI48_512 1 "register_operand" "v,m") + (match_operand:SI 2 "nonmemory_operand" "vN,N")))] + "TARGET_AVX512F" + "vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "avx512f") + (set_attr "type" "sseishft") + (set (attr "length_immediate") + (if_then_else (match_operand 2 "const_int_operand") + (const_string "1") + (const_string "0"))) + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_expand "vec_shl_" [(set (match_operand:VI_128 0 "register_operand") (ashift:V1TI @@ -6216,6 +6296,25 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) +(define_insn "avx512f_v" + [(set (match_operand:VI48_512 0 "register_operand" "=v") + (any_rotate:VI48_512 + (match_operand:VI48_512 1 "register_operand" "v") + (match_operand:VI48_512 2 "nonimmediate_operand" "vm")))] + "TARGET_AVX512F" + "vpv\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512f_" + [(set (match_operand:VI48_512 0 "register_operand" "=v") + (any_rotate:VI48_512 + (match_operand:VI48_512 1 "nonimmediate_operand" "vm") + (match_operand:SI 2 "const_0_to_255_operand")))] + "TARGET_AVX512F" + "vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) (define_expand "3" [(set (match_operand:VI124_256_48_512 0 "register_operand") @@ -6449,6 +6548,28 @@ (set_attr "prefix" "vex") (set_attr "mode" "OI")]) +(define_expand "avx512f_eq3" + [(set (match_operand: 0 "register_operand") + (unspec: + [(match_operand:VI48_512 1 "register_operand") + (match_operand:VI48_512 2 "nonimmediate_operand")] + UNSPEC_MASKED_EQ))] + "TARGET_AVX512F" + "ix86_fixup_binary_operands_no_copy (EQ, mode, operands);") + +(define_insn "avx512f_eq3_1" + [(set (match_operand: 0 "register_operand" "=k") + (unspec: + [(match_operand:VI48_512 1 "register_operand" "%v") + (match_operand:VI48_512 2 "nonimmediate_operand" "vm")] + UNSPEC_MASKED_EQ))] + "TARGET_AVX512F && ix86_binary_operator_ok (EQ, mode, operands)" + "vpcmpeq\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "ssecmp") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "*sse4_1_eqv2di3" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (eq:V2DI @@ -6523,6 +6644,18 @@ (set_attr "prefix" "vex") (set_attr "mode" "OI")]) +(define_insn "avx512f_gt3" + [(set (match_operand: 0 "register_operand" "=k") + (unspec: + [(match_operand:VI48_512 1 "register_operand" "v") + (match_operand:VI48_512 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))] + "TARGET_AVX512F" + "vpcmpgt\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "ssecmp") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "sse2_gt3" [(set (match_operand:VI124_128 0 "register_operand" "=x,x") (gt:VI124_128 @@ -6907,6 +7040,28 @@ ] (const_string "")))]) +(define_insn "avx512f_testm3" + [(set (match_operand: 0 "register_operand" "=k") + (unspec: + [(match_operand:VI48_512 1 "register_operand" "v") + (match_operand:VI48_512 2 "nonimmediate_operand" "vm")] + UNSPEC_TESTM))] + "TARGET_AVX512F" + "vptestm\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512f_testnm3" + [(set (match_operand: 0 "register_operand" "=k") + (unspec: + [(match_operand:VI48_512 1 "register_operand" "v") + (match_operand:VI48_512 2 "nonimmediate_operand" "vm")] + UNSPEC_TESTNM))] + "TARGET_AVX512CD" + "%vptestnm\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral element swizzling @@ -9863,6 +10018,148 @@ (set_attr "btver2_decode" "vector,vector,vector,vector") (set_attr "mode" "TI")]) +(define_expand "avx512pf_gatherpf" + [(unspec + [(match_operand: 0 "register_or_constm1_operand") + (mem: + (match_par_dup 5 + [(match_operand 2 "vsib_address_operand") + (match_operand:VI48_512 1 "register_operand") + (match_operand:SI 3 "const1248_operand")])) + (match_operand:SI 4 "const_0_to_1_operand")] + UNSPEC_GATHER_PREFETCH)] + "TARGET_AVX512PF" +{ + operands[5] + = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, operands[2], operands[1], + operands[3]), UNSPEC_VSIBADDR); +}) + +(define_insn "*avx512pf_gatherpf_mask" + [(unspec + [(match_operand: 0 "register_operand" "k") + (match_operator: 5 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 2 "vsib_address_operand" "p") + (match_operand:VI48_512 1 "register_operand" "v") + (match_operand:SI 3 "const1248_operand" "n")] + UNSPEC_VSIBADDR)]) + (match_operand:SI 4 "const_0_to_1_operand" "n")] + UNSPEC_GATHER_PREFETCH)] + "TARGET_AVX512PF" +{ + switch (INTVAL (operands[4])) + { + case 0: + return "vgatherpf0ps\t{%5%{%0%}|%5%{%0%}}"; + case 1: + return "vgatherpf1ps\t{%5%{%0%}|%5%{%0%}}"; + default: + gcc_unreachable (); + } +} + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + +(define_insn "*avx512pf_gatherpf" + [(unspec + [(const_int -1) + (match_operator: 4 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 1 "vsib_address_operand" "p") + (match_operand:VI48_512 0 "register_operand" "v") + (match_operand:SI 2 "const1248_operand" "n")] + UNSPEC_VSIBADDR)]) + (match_operand:SI 3 "const_0_to_1_operand" "n")] + UNSPEC_GATHER_PREFETCH)] + "TARGET_AVX512PF" +{ + switch (INTVAL (operands[3])) + { + case 0: + return "vgatherpf0ps\t{%4|%4}"; + case 1: + return "vgatherpf1ps\t{%4|%4}"; + default: + gcc_unreachable (); + } +} + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + +(define_expand "avx512pf_scatterpf" + [(unspec + [(match_operand: 0 "register_or_constm1_operand") + (mem: + (match_par_dup 5 + [(match_operand 2 "vsib_address_operand") + (match_operand:VI48_512 1 "register_operand") + (match_operand:SI 3 "const1248_operand")])) + (match_operand:SI 4 "const_0_to_1_operand")] + UNSPEC_SCATTER_PREFETCH)] + "TARGET_AVX512PF" +{ + operands[5] + = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, operands[2], operands[1], + operands[3]), UNSPEC_VSIBADDR); +}) + +(define_insn "*avx512pf_scatterpf_mask" + [(unspec + [(match_operand: 0 "register_operand" "k") + (match_operator: 5 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 2 "vsib_address_operand" "p") + (match_operand:VI48_512 1 "register_operand" "v") + (match_operand:SI 3 "const1248_operand" "n")] + UNSPEC_VSIBADDR)]) + (match_operand:SI 4 "const_0_to_1_operand" "n")] + UNSPEC_SCATTER_PREFETCH)] + "TARGET_AVX512PF" +{ + switch (INTVAL (operands[4])) + { + case 0: + return "vscatterpf0ps\t{%5%{%0%}|%5%{%0%}}"; + case 1: + return "vscatterpf1ps\t{%5%{%0%}|%5%{%0%}}"; + default: + gcc_unreachable (); + } +} + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + +(define_insn "*avx512pf_scatterpf" + [(unspec + [(const_int -1) + (match_operator: 4 "vsib_mem_operator" + [(unspec:P + [(match_operand:P 1 "vsib_address_operand" "p") + (match_operand:VI48_512 0 "register_operand" "v") + (match_operand:SI 2 "const1248_operand" "n")] + UNSPEC_VSIBADDR)]) + (match_operand:SI 3 "const_0_to_1_operand" "n")] + UNSPEC_SCATTER_PREFETCH)] + "TARGET_AVX512PF" +{ + switch (INTVAL (operands[3])) + { + case 0: + return "vscatterpf0ps\t{%4|%4}"; + case 1: + return "vscatterpf1ps\t{%4|%4}"; + default: + gcc_unreachable (); + } +} + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; XOP instructions @@ -10409,6 +10706,13 @@ } }) +(define_expand "vlshr3" + [(set (match_operand:VI48_512 0 "register_operand") + (lshiftrt:VI48_512 + (match_operand:VI48_512 1 "register_operand") + (match_operand:VI48_512 2 "nonimmediate_operand")))] + "TARGET_AVX512F") + (define_expand "vlshr3" [(set (match_operand:VI48_256 0 "register_operand") (lshiftrt:VI48_256 @@ -10476,6 +10780,13 @@ } }) +(define_expand "vashl3" + [(set (match_operand:VI48_512 0 "register_operand") + (ashift:VI48_512 + (match_operand:VI48_512 1 "register_operand") + (match_operand:VI48_512 2 "nonimmediate_operand")))] + "TARGET_AVX512F") + (define_expand "vashl3" [(set (match_operand:VI48_256 0 "register_operand") (ashift:VI48_256 @@ -10994,6 +11305,16 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_insn "avx512f_vec_dup_gpr" + [(set (match_operand:VI48_512 0 "register_operand" "=v") + (vec_duplicate:VI48_512 + (match_operand: 1 "register_operand" "r")))] + "TARGET_AVX512F && (mode != V8DImode || TARGET_64BIT)" + "vpbroadcast\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "avx512f_vec_dup_mem" [(set (match_operand:VI48F_512 0 "register_operand" "=v") (vec_duplicate:VI48F_512 @@ -12140,3 +12461,24 @@ [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) + +(define_insn "clz2" + [(set (match_operand:VI48_512 0 "register_operand" "=v") + (clz:VI48_512 + (match_operand:VI48_512 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX512CD" + "vplzcnt\t{%1, %0|%0, %1}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "conflict" + [(set (match_operand:VI48_512 0 "register_operand" "=v") + (unspec:VI48_512 + [(match_operand:VI48_512 1 "nonimmediate_operand" "vm")] + UNSPEC_CONFLICT))] + "TARGET_AVX512CD" + "vpconflict\t{%1, %0|%0, %1}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")])