From: Andreas Schwab <schwab@suse.de>
Date: Wed, 9 Nov 2016 10:40:00 +0000 (+0000)
Subject: re PR target/78254 (FAIL: g++.dg/torture/pr77822.C   -O3 -g  (internal compiler error))
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ff272319ce8c321e9fc148c2c5edb4b1a268240;p=gcc.git

re PR target/78254 (FAIL: g++.dg/torture/pr77822.C   -O3 -g  (internal compiler error))

PR target/78254
* config/m68k/m68k.md: Reject out-of-range bit pos in bit-fields
insns operating on a register.

From-SVN: r241996
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4b15823670a..7c94651348f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-11-09  Andreas Schwab  <schwab@suse.de>
+
+	PR target/78254
+	* config/m68k/m68k.md: Reject out-of-range bit pos in bit-fields
+	insns operating on a register.
+
 2016-11-09  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/78007
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index ec37bd76f55..3d7895d264c 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -706,7 +706,7 @@
 			       (minus:SI (const_int 31)
 				         (match_operand:SI 1 "general_operand" "di")))
 	     (const_int 0)))]
-  ""
+  "!(CONST_INT_P (operands[1]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
   return output_btst (operands, operands[1], operands[0], insn, 31);
 })
@@ -765,9 +765,10 @@
     (cc0)
     (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do")
 			      (const_int 1)
-			    (match_operand:SI 1 "const_int_operand" "n"))
+			      (match_operand:SI 1 "const_int_operand" "n"))
 	     (const_int 0)))]
-  "!TARGET_COLDFIRE"
+  "!TARGET_COLDFIRE
+   && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
   if (GET_CODE (operands[0]) == MEM)
     {
@@ -790,7 +791,8 @@
 			      (const_int 1)
 			      (match_operand:SI 1 "const_int_operand" "n"))
 	     (const_int 0)))]
-  "TARGET_COLDFIRE"
+  "TARGET_COLDFIRE
+   && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
   if (GET_CODE (operands[0]) == MEM)
     {
@@ -5397,6 +5399,7 @@
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(match_operand:SI 3 "register_operand" "d"))]
   "TARGET_68020 && TARGET_BITFIELD
+   && IN_RANGE (INTVAL (operands[2]), 0, 31)
    && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
    && INTVAL (operands[2]) % INTVAL (operands[1]) == 0"
 {
@@ -5438,6 +5441,7 @@
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
+   && IN_RANGE (INTVAL (operands[3]), 0, 31)
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
 {
@@ -5480,6 +5484,7 @@
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
+   && IN_RANGE (INTVAL (operands[3]), 0, 31)
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
 {
@@ -5610,7 +5615,7 @@
 	(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
   "bfexts %1{%b3:%b2},%0")
 
 (define_insn "*extv_bfextu_reg"
@@ -5618,7 +5623,7 @@
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     {
@@ -5637,7 +5642,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(const_int 0))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
 {
   CC_STATUS_INIT;
   return "bfclr %0{%b2:%b1}";
@@ -5648,7 +5653,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(const_int -1))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
 {
   CC_STATUS_INIT;
   return "bfset %0{%b2:%b1}";
@@ -5659,7 +5664,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(match_operand:SI 3 "register_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
 {
 #if 0
   /* These special cases are now recognized by a specific pattern.  */
@@ -5707,7 +5712,8 @@
 				  (match_operand:SI 1 "const_int_operand" "n")
 			 	  (match_operand:SI 2 "general_operand" "dn"))
 		 (const_int 0)))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD
+    && !(CONST_INT_P (operands[2]) && !IN_RANGE (INTVAL (operands[2]), 0, 31))"
 {
   if (operands[1] == const1_rtx
       && GET_CODE (operands[2]) == CONST_INT)