From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Fri, 10 Jul 2020 08:14:31 +0000 (+0200)
Subject: Fix R/R conflicts
X-Git-Tag: working-ls180~381^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ffaddee5e6422c74fd002f9b1272cfe40839a13;p=yosys.git

Fix R/R conflicts

This commit fixes R/R conflicts introduced by commit 7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index dfdb11cf0..1c86c7895 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1348,13 +1348,6 @@ param_real:
 		astbuf1->children.push_back(new AstNode(AST_REALVALUE));
 	}
 
-param_logic:
-	TOK_LOGIC {
-		// SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned
-		astbuf1->is_signed = false;
-		astbuf1->is_logic = true;
-	}
-
 param_range:
 	range {
 		if ($1 != NULL) {
@@ -1366,10 +1359,8 @@ param_integer_type: param_integer param_signed
 param_range_type: type_vec param_signed param_range
 param_implicit_type: param_signed param_range
 
-param_integer_vector_type: param_logic param_signed param_range
-
 param_type:
-	param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type |
+	param_integer_type | param_real | param_range_type | param_implicit_type |
 	hierarchical_type_id {
 		astbuf1->is_custom_type = true;
 		astbuf1->children.push_back(new AstNode(AST_WIRETYPE));