From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 21 Dec 2020 21:47:07 +0000 (+0000)
Subject: add assembly annotation
X-Git-Tag: convert-csv-opcode-to-binary~1068
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0ffb3b5606c56f47d2fbc6b01f25bee4c2e4eb3e;p=libreriscv.git

add assembly annotation
---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 983887c85..bcb45b431 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -861,3 +861,21 @@ Vectorised (mtspr, bc, dcbz, twi)
 
 TODO generate table which will be here [[svp64/reg_profiles]]
 
+## Assembly Annotation
+
+Assembly code annotation is required for SV to be able to successfully
+mark instructions as "prefixed".
+
+A reasonable (prototype) starting point:
+
+    svp64 [field=value]*
+
+Fields:
+
+* ew=8/16/32 - element width
+* sew=8/16/32 - source element width
+* vec=2/3/4 - SUBVL
+* mode=reduce/satu/sats/crpred
+* pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
+* spred={reg spec}
+