From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 24 Jun 2020 18:18:42 +0000 (-0400)
Subject: Have lsmem handle stall and valid signals correctly
X-Git-Tag: div_pipeline~282
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=100196966cca7b68975789f99c270aa46995d3a5;p=soc.git

Have lsmem handle stall and valid signals correctly
---

diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py
index 6256d0e5..7eec4035 100644
--- a/src/soc/experiment/lsmem.py
+++ b/src/soc/experiment/lsmem.py
@@ -14,20 +14,26 @@ class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+
         m.submodules.mem = mem = TestMemory(
             self.regwid, self.addrwid, granularity=8)
 
+        do_load = Signal()  # set when doing a load while valid and not stalled
+        do_store = Signal() # set when doing a store while valid and not stalled
+
+        m.d.comb += [
+            do_load.eq(self.x_load & (self.x_valid & ~self.x_stall)),
+            do_store.eq(self.x_store & (self.x_valid & ~self.x_stall)),
+            ]
         m.d.comb += [
             mem.rdport.addr.eq(self.x_addr[2:]),
             self.m_load_data.eq(mem.rdport.data),
 
             mem.wrport.addr.eq(self.x_addr[2:]),
-            mem.wrport.en.eq(Mux(self.x_store, self.x_mask, 0)),
+            mem.wrport.en.eq(Mux(do_store, self.x_mask, 0)),
             mem.wrport.data.eq(self.x_store_data)
             ]
 
-        m.d.sync += self.x_valid.eq(self.x_load)
-
         return m
 
 
@@ -36,7 +42,12 @@ def write_to_addr(dut, addr, value):
     yield dut.x_store_data.eq(value)
     yield dut.x_store.eq(1)
     yield dut.x_mask.eq(-1)
-
+    yield dut.x_valid.eq(1)
+    yield dut.x_stall.eq(1)
+    yield
+    yield
+    
+    yield dut.x_stall.eq(0)
     yield
     yield dut.x_store.eq(0)
     while (yield dut.x_stall):
@@ -45,6 +56,10 @@ def write_to_addr(dut, addr, value):
 def read_from_addr(dut, addr):
     yield dut.x_addr.eq(addr)
     yield dut.x_load.eq(1)
+    yield dut.x_valid.eq(1)
+    yield dut.x_stall.eq(1)
+    yield
+    yield dut.x_stall.eq(0)
     yield
     yield dut.x_load.eq(0)
     yield Settle()
@@ -59,6 +74,7 @@ def write_byte(dut, addr, val):
     yield dut.x_store.eq(1)
     yield dut.x_store_data.eq(val << (offset * 8))
     yield dut.x_mask.eq(1 << offset)
+    yield dut.x_valid.eq(1)
 
     yield
     yield dut.x_store.eq(0)
@@ -69,6 +85,7 @@ def read_byte(dut, addr):
     offset = addr & 0x3
     yield dut.x_addr.eq(addr)
     yield dut.x_load.eq(1)
+    yield dut.x_valid.eq(1)
     yield
     yield dut.x_load.eq(0)
     yield Settle()