From: Luke Kenneth Casson Leighton Date: Fri, 19 Jun 2020 10:21:09 +0000 (+0100) Subject: take only matching parts of "undefined" variable in mod/div X-Git-Tag: convert-csv-opcode-to-binary~2434 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=101f5f7b3341dcec1ec7a59b413d2d23607e9a30;p=libreriscv.git take only matching parts of "undefined" variable in mod/div --- diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn index 893a9b915..5f5a33e8d 100644 --- a/openpower/isa/fixedarith.mdwn +++ b/openpower/isa/fixedarith.mdwn @@ -291,7 +291,7 @@ XO-Form prod[0:63] <- (RA)[32:63] * (RB)[32:63] RT[32:63] <- prod[0:31] - RT[0:31] <- undefined + RT[0:31] <- undefined[0:31] Special Registers Altered: @@ -322,7 +322,7 @@ XO-Form prod[0:63] <- (RA)[32:63] * (RB)[32:63] RT[32:63] <- prod[0:31] - RT[0:31] <- undefined + RT[0:31] <- undefined[0:31] Special Registers Altered: @@ -340,7 +340,7 @@ XO-Form dividend[0:31] <- (RA)[32:63] divisor[0:31] <- (RB) [32:63] RT[32:63] <- dividend / divisor - RT[0:31] <- undefined + RT[0:31] <- undefined[0:31] Special Registers Altered: @@ -359,7 +359,7 @@ XO-Form dividend[0:31] <- (RA)[32:63] divisor[0:31] <- (RB)[32:63] RT[32:63] <- dividend / divisor - RT[0:31] <- undefined + RT[0:31] <- undefined[0:31] Special Registers Altered: @@ -378,7 +378,7 @@ XO-Form dividend[0:63] <- (RA)[32:63] || [0]*32 divisor[0:31] <- (RB)[32:63] RT[32:63] <- dividend / divisor - RT[0:31] <- undefined + RT[0:31] <- undefined[0:31] Special Registers Altered: @@ -397,7 +397,7 @@ XO-Form dividend[0:63] <- (RA)[32:63] || [0]*32 divisor[0:31] <- (RB)[32:63] RT[32:63] <- dividend / divisor - RT[0:31] <- undefined + RT[0:31] <- undefined[0:31] Special Registers Altered: @@ -413,7 +413,7 @@ X-Form dividend[0:31] <- (RA)[32:63] divisor [0:31] <- (RB)[32:63]- RT[32:63] <- dividend % divisor - RT[0:31 ] <- undefined + RT[0:31 ] <- undefined[0:31] Special Registers Altered: @@ -428,7 +428,7 @@ X-Form dividend[0:31] <- (RA) [32:63] divisor [0:31] <- (RB) [32:63] RT[32:63] <- dividend % divisor - RT[0:31 ] <- undefined + RT[0:31 ] <- undefined[0:31] Special Registers Altered: