From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 19:31:32 +0000 (+0100)
Subject: add link to bugreport in CR pipe formal test
X-Git-Tag: div_pipeline~1007
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1038758d510f65730cdd8ac44e42436a8271cec7;p=soc.git

add link to bugreport in CR pipe formal test
---

diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py
index 18d0d1d8..79c16103 100644
--- a/src/soc/fu/cr/formal/proof_main_stage.py
+++ b/src/soc/fu/cr/formal/proof_main_stage.py
@@ -1,5 +1,9 @@
 # Proof of correctness for partitioned equal signal combiner
 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+"""
+Links:
+* https://bugs.libre-soc.org/show_bug.cgi?id=332
+"""
 
 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
                     signed, Array)