From: Michael Nolan <mtnolan2640@gmail.com>
Date: Fri, 15 May 2020 15:27:42 +0000 (-0400)
Subject: Add test for cntlz to test_caller
X-Git-Tag: div_pipeline~1194
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=103c228703a400f3a05917be11b493249757ce4e;p=soc.git

Add test for cntlz to test_caller
---

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 2c135361..f1563472 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -254,6 +254,16 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(4),
                              SelectableInt(0x2b, 64))
 
+    def test_cntlz(self):
+        lst = ["cntlzd 2, 1",
+               "cntlzw 4, 3"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x0000beeecaffc0de
+        initial_regs[3] = 0x0000000000ffc0de
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(2), SelectableInt(16, 64))
+            self.assertEqual(sim.gpr(4), SelectableInt(8, 64))
         
 
     def test_mtcrf(self):