From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 10 Oct 2019 19:35:06 +0000 (+0200)
Subject: cpu: add buses list and use it in soc_core to add bus masters
X-Git-Tag: 24jan2021_ls180~924
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1045cda39e63b3bfcf1d24d26dbc15837e25d9e3;p=litex.git

cpu: add buses list and use it in soc_core to add bus masters
---

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 3cda5a19..8bc86829 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -34,6 +34,7 @@ class Minerva(CPU):
         self.reset     = Signal()
         self.ibus      = wishbone.Interface()
         self.dbus      = wishbone.Interface()
+        self.buses     = [self.ibus, self.dbus]
         self.interrupt = Signal(32)
 
         # # #
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 16a43e89..954401bd 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -63,11 +63,12 @@ class MOR1KX(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform = platform
-        self.variant  = variant
+        self.platform  = platform
+        self.variant   = variant
         self.reset     = Signal()
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()
+        self.buses     = [i, d]
         self.interrupt = Signal(32)
 
         if variant == "linux":
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index c9b3af5f..a190cb77 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -60,6 +60,7 @@ class PicoRV32(CPU):
         self.reset     = Signal()
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()
+        self.buses     = [i, d]
         self.interrupt = Signal(32)
         self.trap      = Signal()
 
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index c9fdb0dd..3a7320c5 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -94,6 +94,8 @@ class RocketRV64(CPU):
         self.ibus = ibus = wishbone.Interface()
         self.dbus = dbus = wishbone.Interface()
 
+        self.buses = [ibus, dbus]
+
         # # #
 
         self.cpu_params = dict(
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 375dd9a9..2accda02 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -102,10 +102,11 @@ class VexRiscv(CPU, AutoCSR):
         self.platform         = platform
         self.variant          = variant
         self.external_variant = None
-        self.reset     = Signal()
-        self.ibus      = ibus = wishbone.Interface()
-        self.dbus      = dbus = wishbone.Interface()
-        self.interrupt = Signal(32)
+        self.reset      = Signal()
+        self.ibus       = ibus = wishbone.Interface()
+        self.dbus       = dbus = wishbone.Interface()
+        self.buses      = [ibus, dbus]
+        self.interrupt  = Signal(32)
 
         self.cpu_params = dict(
                 i_clk=ClockSignal(),
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 55278bbc..0284252f 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -182,9 +182,9 @@ class SoCCore(Module):
             self.cpu.set_reset_address(self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address)
             self.config["CPU_RESET_ADDR"] = self.cpu.reset_address
 
-            # Add Instruction/Data buses as Wisbone masters
-            self.add_wb_master(self.cpu.ibus)
-            self.add_wb_master(self.cpu.dbus)
+            # Add CPU buses as Wisbone masters
+            for bus in self.cpu.buses:
+                self.add_wb_master(bus)
 
             # Add CPU CSR (dynamic)
             self.add_csr("cpu", allow_user_defined=True)