From: Michael Walle <michael@walle.cc>
Date: Mon, 12 Nov 2012 18:36:14 +0000 (+0100)
Subject: lm32: rename mem array in lm32_dp_ram
X-Git-Tag: 24jan2021_ls180~3080
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10495e72d00a3d940430ed5f04edf455cdb734a8;p=litex.git

lm32: rename mem array in lm32_dp_ram

Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.

Signed-off-by: Michael Walle <michael@walle.cc>
---

diff --git a/verilog/lm32/lm32_dp_ram.v b/verilog/lm32/lm32_dp_ram.v
index 1d7f4f17..6ef952ab 100644
--- a/verilog/lm32/lm32_dp_ram.v
+++ b/verilog/lm32/lm32_dp_ram.v
@@ -19,15 +19,15 @@ input [data_width-1:0] wdata_i;
 input [addr_width-1:0] raddr_i;
 output [data_width-1:0] rdata_o;
 
-reg [data_width-1:0] ram[addr_depth-1:0];
+reg [data_width-1:0] mem[addr_depth-1:0];
 
 reg [addr_width-1:0] raddr_r;
-assign rdata_o = ram[raddr_r];
+assign rdata_o = mem[raddr_r];
 
 always @ (posedge clk_i)
 begin
 	if (we_i)
-		ram[waddr_i] <= wdata_i;
+		mem[waddr_i] <= wdata_i;
 	raddr_r <= raddr_i;
 end