From: lkcl <lkcl@web>
Date: Sun, 14 Aug 2022 12:55:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~862
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1058b1809077260a6f4d18288eda7f924e698d04;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index e3587859e..f553aaf2e 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -191,7 +191,10 @@ extsw: there is no artificial limit.
 
 The only major caveat is that the registers to be used as
 Indices must not be modified by any instruction after Indexed Mode
-is established, and neither must MAXVL be altered. Failure to observe
+is established, and neither must MAXVL be altered. Additionally,
+no register used as an Index may exceed MAXVL.
+
+Failure to observe
 these conditions results in `UNDEFINED` behaviour.
 These conditions allow a Read-After-Write (RAW) Hazard to be created on
 the entire range of Indices to be subsequently used, but a corresponding
@@ -423,6 +426,7 @@ whilst `mm=1` is intended to be a little more refined.
 Beyond these mappings it becomes necessary to write directly to
 the SVSTATE SPRs manually.
 
+
 # TODO
 
 * investigate https://www.ncbi.nlm.nih.gov/pmc/articles/PMC6879380/#!po=19.6429