From: Matthew Wahab Date: Tue, 12 Jan 2016 16:35:30 +0000 (+0000) Subject: [ARM] Support ARMv8.2 RAS extension. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=105bde5771c1c1b26b69e3623c88f3caafa3a480;p=binutils-gdb.git [ARM] Support ARMv8.2 RAS extension. The ARMv8.2 architecture includes the RAS extension which adds an instruction, ESB, and a number of coprocessor registers. This patch adds the instruction to binutils, making it available when -march=armv8.2-a is selected. It also adds tests for the instruction and for the coprocessor registers. gas/ 2016-01-12 Matthew Wahab * config/tc-arm.c (arm_ext_v8_2): New. (insns): Add "esb". * testsuite/gas/arm/armv8_2-a.d: New. * testsuite/gas/arm/armv8_2-a.s: New. opcodes/ 2016-01-12 Matthew Wahab * arm-dis.c (arm_opcodes): Add "esb". (thumb_opcodes): Likewise. Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34 --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 59a04730fc1..4db90f65ad0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2016-01-12 Matthew Wahab + + * config/tc-arm.c (arm_ext_v8_2): New. + (insns): Add "esb". + * testsuite/gas/arm/armv8_2-a.d: New. + * testsuite/gas/arm/armv8_2-a.s: New. + 2016-01-12 Alan Modra * testsuite/gas/ppc/vsx3.d: Accept nop padding. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 0edc01aa9e8..046abe5b9e6 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -214,6 +214,8 @@ static const arm_feature_set arm_ext_v6t2_v8m = /* Instructions shared between ARMv8-A and ARMv8-M. */ static const arm_feature_set arm_ext_atomics = ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS); +static const arm_feature_set arm_ext_v8_2 = + ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A); static const arm_feature_set arm_arch_any = ARM_ANY; static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1); @@ -19340,6 +19342,13 @@ static const struct asm_opcode insns[] = TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch), TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw), + /* ARMv8.2 RAS extension. */ +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v8_2 +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v8_2 + TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs), + #undef ARM_VARIANT #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ #undef THUMB_VARIANT diff --git a/gas/testsuite/gas/arm/armv8_2-a.d b/gas/testsuite/gas/arm/armv8_2-a.d new file mode 100644 index 00000000000..92845de5db6 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_2-a.d @@ -0,0 +1,51 @@ +#name: ARMv8.2-A +#objdump: -dr + +.*: +file format .*arm.* + +Disassembly of section .text: + +[0-9a-f]+ <.*>: + [0-9a-f]+: e320f010 esb + +[0-9a-f]+ <.*>: + [0-9a-f]+: f3af 8010 esb + +[0-9a-f]+ <.*>: + [0-9a-f]+: ee100f11 mrc 15, 0, r0, cr0, cr1, \{0\} + [0-9a-f]+: ee100fd2 mrc 15, 0, r0, cr0, cr2, \{6\} + [0-9a-f]+: ee150f13 mrc 15, 0, r0, cr5, cr3, \{0\} + [0-9a-f]+: ee150f33 mrc 15, 0, r0, cr5, cr3, \{1\} + [0-9a-f]+: ee051f33 mcr 15, 0, r1, cr5, cr3, \{1\} + [0-9a-f]+: ee150f14 mrc 15, 0, r0, cr5, cr4, \{0\} + [0-9a-f]+: ee150f34 mrc 15, 0, r0, cr5, cr4, \{1\} + [0-9a-f]+: ee051f34 mcr 15, 0, r1, cr5, cr4, \{1\} + [0-9a-f]+: ee150f54 mrc 15, 0, r0, cr5, cr4, \{2\} + [0-9a-f]+: ee051f54 mcr 15, 0, r1, cr5, cr4, \{2\} + [0-9a-f]+: ee150f74 mrc 15, 0, r0, cr5, cr4, \{3\} + [0-9a-f]+: ee051f74 mcr 15, 0, r1, cr5, cr4, \{3\} + [0-9a-f]+: ee150f94 mrc 15, 0, r0, cr5, cr4, \{4\} + [0-9a-f]+: ee150fb4 mrc 15, 0, r0, cr5, cr4, \{5\} + [0-9a-f]+: ee051fb4 mcr 15, 0, r1, cr5, cr4, \{5\} + [0-9a-f]+: ee150ff4 mrc 15, 0, r0, cr5, cr4, \{7\} + [0-9a-f]+: ee051ff4 mcr 15, 0, r1, cr5, cr4, \{7\} + [0-9a-f]+: ee150f15 mrc 15, 0, r0, cr5, cr5, \{0\} + [0-9a-f]+: ee051f15 mcr 15, 0, r1, cr5, cr5, \{0\} + [0-9a-f]+: ee150f35 mrc 15, 0, r0, cr5, cr5, \{1\} + [0-9a-f]+: ee051f35 mcr 15, 0, r1, cr5, cr5, \{1\} + [0-9a-f]+: ee150f95 mrc 15, 0, r0, cr5, cr5, \{4\} + [0-9a-f]+: ee051f95 mcr 15, 0, r1, cr5, cr5, \{4\} + [0-9a-f]+: ee150fb5 mrc 15, 0, r0, cr5, cr5, \{5\} + [0-9a-f]+: ee051fb5 mcr 15, 0, r1, cr5, cr5, \{5\} + [0-9a-f]+: ee1c0f31 mrc 15, 0, r0, cr12, cr1, \{1\} + [0-9a-f]+: ee0c1f31 mcr 15, 0, r1, cr12, cr1, \{1\} + [0-9a-f]+: ee910f91 mrc 15, 4, r0, cr1, cr1, \{4\} + [0-9a-f]+: ee811f91 mcr 15, 4, r1, cr1, cr1, \{4\} + [0-9a-f]+: ee950f72 mrc 15, 4, r0, cr5, cr2, \{3\} + [0-9a-f]+: ee851f72 mcr 15, 4, r1, cr5, cr2, \{3\} + [0-9a-f]+: ee910f31 mrc 15, 4, r0, cr1, cr1, \{1\} + [0-9a-f]+: ee811f31 mcr 15, 4, r1, cr1, cr1, \{1\} + [0-9a-f]+: ee9c0f31 mrc 15, 4, r0, cr12, cr1, \{1\} + [0-9a-f]+: ee8c1f31 mcr 15, 4, r1, cr12, cr1, \{1\} + [0-9a-f]+: eed10f11 mrc 15, 6, r0, cr1, cr1, \{0\} + [0-9a-f]+: eec11f11 mcr 15, 6, r1, cr1, cr1, \{0\} diff --git a/gas/testsuite/gas/arm/armv8_2-a.s b/gas/testsuite/gas/arm/armv8_2-a.s new file mode 100644 index 00000000000..a27ac638f41 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_2-a.s @@ -0,0 +1,44 @@ + /* ARMv8.2 features. */ + + /* RAS instructions. */ +A1: + .arm + esb +T1: .thumb + esb + + /* RAS system registers. */ + .macro test_sysreg Opc1 CRn CRm Opc2 rw + mrc p15, \Opc1,\() r0, \CRn\(), \CRm\(), \Opc2\() + .if \rw + mcr p15, \Opc1\(), r1, \CRn\(), \CRm\(), \Opc2\() + .endif + .endm + +A2: + .arm + test_sysreg 0 c0 c1 0 0 + test_sysreg 0 c0 c2 6 0 + test_sysreg 0 c5 c3 0 0 + test_sysreg 0 c5 c3 1 1 + + test_sysreg 0 c5 c4 0 0 + test_sysreg 0 c5 c4 1 1 + test_sysreg 0 c5 c4 2 1 + test_sysreg 0 c5 c4 3 1 + test_sysreg 0 c5 c4 4 0 + test_sysreg 0 c5 c4 5 1 + test_sysreg 0 c5 c4 7 1 + + test_sysreg 0 c5 c5 0 1 + test_sysreg 0 c5 c5 1 1 + test_sysreg 0 c5 c5 4 1 + test_sysreg 0 c5 c5 5 1 + + test_sysreg 0 c12 c1 1 1 + test_sysreg 4 c1 c1 4 1 + test_sysreg 4 c5 c2 3 1 + test_sysreg 4 c1 c1 1 1 + test_sysreg 4 c12 c1 1 1 + + test_sysreg 6 c1 c1 0 1 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6ccfdb7c412..333bac5a64c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-01-12 Matthew Wahab + + * arm-dis.c (arm_opcodes): Add "esb". + (thumb_opcodes): Likewise. + 2016-01-11 Peter Bergner * ppc-opc.c : Delete. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 2695101b4bd..56da264739b 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1576,6 +1576,10 @@ static const struct opcode32 arm_opcodes[] = 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + /* V8.2 RAS extension instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A), + 0xe320f010, 0xffffffff, "esb"}, + /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0x0320f005, 0x0fffffff, "sevl"}, @@ -2532,6 +2536,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, + /* ARM V8.2 RAS extension instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A), + 0xf3af8010, 0xffffffff, "esb"}, + /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3af8005, 0xffffffff, "sevl%c.w"},