From: whitequark Date: Fri, 15 Feb 2019 14:15:02 +0000 (+0000) Subject: tracer: factor out get_var_name(default=). X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1076a4b129e35dafd7a7e9278d7d1dae040eb78f;p=nmigen.git tracer: factor out get_var_name(default=). --- diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index 3dd8809..e7fc288 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -581,12 +581,7 @@ class Signal(Value, DUID): attrs=None, decoder=None, src_loc_at=0): super().__init__(src_loc_at=src_loc_at) - if name is None: - try: - name = tracer.get_var_name(depth=2 + src_loc_at) - except tracer.NameNotFound: - name = "$signal" - self.name = name + self.name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$signal") if shape is None: if min is None: @@ -625,12 +620,8 @@ class Signal(Value, DUID): other : Value Object to base this Signal on. """ - if name is None: - try: - name = tracer.get_var_name(depth=2 + src_loc_at) - except tracer.NameNotFound: - name = "$like" - kw = dict(shape=cls.wrap(other).shape(), name=name) + name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$like") + kw = dict(shape=cls.wrap(other).shape(), name=name) if isinstance(other, cls): kw.update(reset=other.reset, reset_less=other.reset_less, attrs=other.attrs, decoder=other.decoder) diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 0d86ac4..bef8035 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -15,12 +15,7 @@ class Memory: raise TypeError("Memory depth must be a non-negative integer, not '{!r}'" .format(depth)) - if name is None: - try: - name = tracer.get_var_name(depth=2) - except tracer.NameNotFound: - name = "$memory" - self.name = name + self.name = name or tracer.get_var_name(depth=2, default="$memory") self.src_loc = tracer.get_src_loc() self.width = width @@ -194,10 +189,7 @@ class DummyPort: if granularity is None: granularity = width if name is None: - try: - name = tracer.get_var_name(depth=2) - except tracer.NameNotFound: - name = "dummy" + name = tracer.get_var_name(depth=2, default="dummy") self.addr = Signal(addr_bits, name="{}_addr".format(name)) diff --git a/nmigen/hdl/rec.py b/nmigen/hdl/rec.py index 0b06f75..999c85b 100644 --- a/nmigen/hdl/rec.py +++ b/nmigen/hdl/rec.py @@ -64,10 +64,8 @@ class Layout: class Record(Value): def __init__(self, layout, name=None): if name is None: - try: - name = tracer.get_var_name() - except tracer.NameNotFound: - pass + name = tracer.get_var_name(default=None) + self.name = name self.src_loc = tracer.get_src_loc() diff --git a/nmigen/tracer.py b/nmigen/tracer.py index 225ee1a..49c9650 100644 --- a/nmigen/tracer.py +++ b/nmigen/tracer.py @@ -10,7 +10,10 @@ class NameNotFound(Exception): pass -def get_var_name(depth=2): +_raise_exception = object() + + +def get_var_name(depth=2, default=_raise_exception): frame = inspect.currentframe() for _ in range(depth): frame = frame.f_back @@ -37,7 +40,10 @@ def get_var_name(depth=2): "DUP_TOP", "BUILD_LIST"): index += 2 else: - raise NameNotFound + if default is _raise_exception: + raise NameNotFound + else: + return default def get_src_loc(src_loc_at=0):