From: Cesar Strauss <cestrauss@gmail.com>
Date: Thu, 2 Jul 2020 08:55:59 +0000 (-0300)
Subject: Present the ALU result only when valid_o is active
X-Git-Tag: div_pipeline~179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10833548e34e3fc6dfa9b6b6bf19b62a2f8b570f;p=soc.git

Present the ALU result only when valid_o is active

This should help to catch latching of invalid data.
Also, better demonstrates the valid / ready protocol.
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 581fd113..5dcf958c 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -268,7 +268,8 @@ class ALU(Elaboratable):
         # choose between zero-delay output, or registered
         with m.If(go_now):
             m.d.comb += self.o.eq(sub.o)
-        with m.Else():
+        # only present the result at the last computation cycle
+        with m.Elif(alu_done):
             m.d.comb += self.o.eq(alu_r)
 
         return m