From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 9 Mar 2020 16:12:30 +0000 (+0000)
Subject: update LDSTCompUnit comments
X-Git-Tag: div_pipeline~1740
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1093fde2f8c5fbea8e338670963bd8b85a319c1c;p=soc.git

update LDSTCompUnit comments
---

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index 6af98f5a..6a8cb358 100644
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -60,6 +60,23 @@ class LDSTCompUnit(Elaboratable):
         * :go_ad_i:    address is being actioned (triggers actual mem LD)
         * :go_st_i:    store is being actioned (triggers actual mem STORE)
         * :go_die_i:   resets the unit back to "wait for issue"
+
+        Control Signals (Out)
+        ---------------------
+
+        * :busy_o:      function unit is busy
+        * :rd_rel_o:    request src1/src2
+        * :adr_rel_o:   request address (from mem)
+        * :sto_rel_o:   request store (to mem)
+        * :req_rel_o:   request write (result)
+
+        Note: adr_rel, sto_rel, req_rel must all be acknowledged in a
+        single cycle.
+
+        Control Data (out)
+        ------------------
+        * :data_o:     Dest out (LD or ALU)
+        * :addr_o:     Address out (LD or ST)
     """
     def __init__(self, rwid, opwid, alu, mem):
         self.opwid = opwid
@@ -90,7 +107,7 @@ class LDSTCompUnit(Elaboratable):
         self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
         self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST)
 
-        # hmm... TODO... move these to outside of LDSTCompUnit
+        # hmm... TODO... move these to outside of LDSTCompUnit?
         self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
         self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
         self.ld_o = Signal(reset_less=True) # operation is a LD