From: lkcl <lkcl@web>
Date: Wed, 30 Mar 2022 10:50:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2949
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1094b2f3697e5fec9a5ddb5989fffeab17538c63;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index fd93c4fbc..6bf8bd0fb 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -73,9 +73,9 @@ OPF ISA WG):
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |
 |19 |RT   |  |mask |BFA  |     |XO[0:4]|XO[5:9]|/ |          |
 |19 |RT   |M |mask |BFA  | 0 0 |XO[0:4]|0 mode |Rc|crrweird  |
-|19 |RA   |/ |mask |BF   | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
-|19 |BFT//|M |mask |BFA  | 1 0 |XO[0:4]|0 mode |/ |crweird   |
-|19 |BF   |/ |mask |BFA  | 1 1 |XO[0:4]|0 mode |/ |crweirder |
+|19 |RA   |M |mask |BF   | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
+|19 |BFT//|M |mask |BFA  | 1 0 |XO[0:4]|0 mode |/ |crweirder |
+|19 |BF   |M |mask |BFA  | 1 1 |XO[0:4]|0 mode |/ |crweird   |
 
 **crrweird**
 
@@ -83,7 +83,7 @@ mode is encoded in XO and is 4 bits
 
 bit 19=0, bit 20=0
 
-    crrweird: RT, BFA, mask.mode
+    crrweird: RT, BFA, M, mask.mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
@@ -102,7 +102,7 @@ such can use Rc=1 and RC1 Data-dependent Mode capability
 
 bit 19=0, bit 20=1
 
-    mtcrweird: BF, RA, mask.mode
+    mtcrweird: BF, RA, M, mask.mode
 
     reg = (RA|0)
     lsb = reg[63] # MSB0 numbering
@@ -110,28 +110,46 @@ bit 19=0, bit 20=1
     n1 = mask[1] & (mode[1] == lsb)
     n2 = mask[2] & (mode[2] == lsb)
     n3 = mask[3] & (mode[3] == lsb)
-    CR{BF} = n0 || n1 || n2 || n3
+    result = n0 || n1 || n2 || n3
+    if M:
+        result |= CR{BF} & ~mask
+    CR{BF} = result
+
+Note that when M=1 this operation is a Read-Modify-Write on the CR Field
+BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
+M=1. Correspondingly when M=0 this operation is an overwrite: no read
+of BF is required because the masked-out bits of the BF CR Field are
+set to zero.
 
 When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
 3-bit Data-dependent and 3-bit Predicate-result capability
-(BT is 3 bits)
+(BF is 3 bits)
 
 **crweird**
 
 bit 19=1, bit 20=0
 
-    crweird: BF, BFA, mask.mode
+    crweird: BF, BFA, M, mask.mode
 
     creg = CR{BFA}
     n0 = mask[0] & (mode[0] == creg[0])
     n1 = mask[1] & (mode[1] == creg[1])
     n2 = mask[2] & (mode[2] == creg[2])
     n3 = mask[3] & (mode[3] == creg[3])
-    CR{BF} = n0 || n1 || n2 || n3
+    result = n0 || n1 || n2 || n3
+    if M:
+        result |= CR{BF} & ~mask
+    CR{BF} = result
+
+Note that when M=1 this operation is a Read-Modify-Write on the CR Field
+BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
+M=1. Correspondingly when M=0 this operation is an overwrite: no read
+of BF is required because the masked-out bits of the BF CR Field are
+set to zero.
 
 When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
 3-bit Data-dependent and 3-bit Predicate-result capability
-(BT is 3 bits)
+(BF is 3 bits)
 
 **crweirder**
 
@@ -155,9 +173,9 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper
 
 **Example Pseudo-ops:**
 
-    mtcri BFA, mode    mtcrweird r0, BFA, 0b1111.~mode
-    mtcrset BFA, mask  mtcrweird r0, BFA, mask.0b0000
-    mtcrclr BFA, mask  mtcrweird r0, BFA, mask.0b1111
+    mtcri BF, mode    mtcrweird BF, r0, 0, 0b1111.~mode
+    mtcrset BF, mask  mtcrweird BF, r0, 1, mask.0b0000
+    mtcrclr BF, mask  mtcrweird BF, r0, 1, mask.0b1111
 
 # Vectorised versions