From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Mar 2013 09:23:02 +0000 (+0100)
Subject: Added [[CITE]] tags to abc and fsm_extract passes
X-Git-Tag: yosys-0.2.0~719
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10956cb84aa7c3dd2300794b9283951dece9e5fa;p=yosys.git

Added [[CITE]] tags to abc and fsm_extract passes
---

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index a51557a4e..acd935465 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -17,6 +17,14 @@
  *
  */
 
+// [[CITE]] ABC
+// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
+// http://www.eecs.berkeley.edu/~alanmi/abc/
+
+// [[CITE]] Kahn's Topological sorting algorithm
+// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025
+// http://en.wikipedia.org/wiki/Topological_sorting
+
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
 #include "kernel/log.h"
@@ -187,6 +195,7 @@ static void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edge
 static void handle_loops()
 {
 	// http://en.wikipedia.org/wiki/Topological_sorting
+	// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
 
 	std::map<int, std::set<int>> edges;
 	std::vector<int> in_edges_count(signal_list.size());
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 4971e4c19..103093165 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -17,6 +17,11 @@
  *
  */
 
+// [[CITE]]
+// Yiqiong Shi; Chan Wai Ting; Bah-Hwee Gwee; Ye Ren, "A highly efficient method for extracting FSMs from flattened gate-level netlist,"
+// Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on , vol., no., pp.2610,2613, May 30 2010-June 2 2010
+// doi: 10.1109/ISCAS.2010.5537093
+
 #include "kernel/log.h"
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
@@ -283,7 +288,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	fsm_cell->connections["\\CTRL_IN"] = ctrl_in;
 	fsm_cell->connections["\\CTRL_OUT"] = ctrl_out;
 	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
-    fsm_cell->attributes = wire->attributes;
+	fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
 	module->cells[fsm_cell->name] = fsm_cell;