From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Fri, 17 Apr 2020 06:16:59 +0000 (+0000)
Subject: Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
X-Git-Tag: working-ls180~619^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10a814f97808de8cce7e50a03f01832db66c263e;p=yosys.git

Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 7447ab8d5..f762f9025 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1924,11 +1924,13 @@ always_events:
 always_event:
 	TOK_POSEDGE expr {
 		AstNode *node = new AstNode(AST_POSEDGE);
+		SET_AST_NODE_LOC(node, @1, @1);
 		ast_stack.back()->children.push_back(node);
 		node->children.push_back($2);
 	} |
 	TOK_NEGEDGE expr {
 		AstNode *node = new AstNode(AST_NEGEDGE);
+		SET_AST_NODE_LOC(node, @1, @1);
 		ast_stack.back()->children.push_back(node);
 		node->children.push_back($2);
 	} |