From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Nov 2013 20:47:08 +0000 (+0100)
Subject: Fixed temp net name generation in rtlil process generator for abbreviated name matching
X-Git-Tag: yosys-0.2.0~282
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10aa08dca171f6d337a3347467a388291445d868;p=yosys.git

Fixed temp net name generation in rtlil process generator for abbreviated name matching
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 8aea05969..1453d13a9 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -361,6 +361,8 @@ struct AST_INTERNAL::ProcessGenerator
 			do {
 				wire->name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
 						chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
+				if (chunk.wire->name.find('$') != std::string::npos)
+					wire->name += stringf("$%d", RTLIL::autoidx++);
 			} while (current_module->wires.count(wire->name) > 0);
 			wire->width = chunk.width;
 			current_module->wires[wire->name] = wire;