From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 19 May 2018 16:52:31 +0000 (+0100)
Subject: more slides
X-Git-Tag: convert-csv-opcode-to-binary~5362
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10b98799ef5b786c8ca8a5008490bf6e0c65a451;p=libreriscv.git

more slides
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 4fe915a8f..0abd3c444 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -87,11 +87,11 @@
 \frametitle{ADD pseudocode (or trap, or actual hardware loop)}
 
 \begin{semiverbatim}
-function op_add(rd, rs1, rs2, predr) \{
+function op_add(rd, rs1, rs2, predr) \{ # add not PADD!
   int i, id=0, irs1=0, irs2=0;
   for (i=0; i < MIN(VL, vectorlen[rd]); i++)
-    if (predicate[predr][i]) # integer regfile: bitfield
-       x[rd+id] <= x[rs1+irs1] + x[rs2+irs2];
+    if (ireg[predr] & 1<<i) # predication uses intregs
+       ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
     # now increment idxs: src/dest all vec/scalar
     if (reg_is_vectorised[rd]) \{ id += 1; \}
     if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}