From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Feb 2020 20:23:36 +0000 (+0000)
Subject: add minor 19 opcode
X-Git-Tag: convert-csv-opcode-to-binary~3278
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10cf0ce7a4f52659ca7de6c94853368e7fa4c49b;p=libreriscv.git

add minor 19 opcode
---

diff --git a/openpower/isatables.mdwn b/openpower/isatables.mdwn
index 3e594eb99..a3b660e1b 100644
--- a/openpower/isatables.mdwn
+++ b/openpower/isatables.mdwn
@@ -6,3 +6,7 @@ TODO
 
 [[!table format=csv file="openpower/isatables/major.csv"]]
 
+## Minor opcode 19
+
+[[!table format=csv file="openpower/isatables/minor_19.csv"]]
+
diff --git a/openpower/isatables/minor_19.csv b/openpower/isatables/minor_19.csv
new file mode 100644
index 000000000..f8517ef94
--- /dev/null
+++ b/openpower/isatables/minor_19.csv
@@ -0,0 +1,5 @@
+--, unit, internal op, in1, in2, in3, out, CR in, CR out, inv A, inv out, cry in, cry out, ldst len, BR, sgn ext, upd, rsrv, 32b, sgn, rc, lk, sgl pipe
+0b000,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mcrf; and cr logical ops
+0b001,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,add pcis not implemented yet
+0b100,ALU,OP_BCREG,SPR,SPR,NONE,SPR,1,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bclr bcctr bctar
+0b111,ALU,OP_ISYNC,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isync