From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 7 Jun 2019 22:17:34 +0000 (+0100)
Subject: extend ld/st mem test
X-Git-Tag: div_pipeline~1885
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10d03c84a80b2ebf7cb6034bdb47ecc45e404283;p=soc.git

extend ld/st mem test
---

diff --git a/src/scoreboard/test_mem_fu_matrix.py b/src/scoreboard/test_mem_fu_matrix.py
index 43cdf07f..015368fa 100644
--- a/src/scoreboard/test_mem_fu_matrix.py
+++ b/src/scoreboard/test_mem_fu_matrix.py
@@ -641,12 +641,29 @@ def test_scoreboard():
     #                    vcd_name='test_scoreboard6600.vcd')
 
 
+def mem_sim(dut):
+    yield dut.ld_i.eq(0x1)
+    yield dut.fn_issue_i.eq(0x1)
+    yield
+    yield dut.st_i.eq(0x2)
+    yield dut.fn_issue_i.eq(0x2)
+    yield
+    yield dut.fn_issue_i.eq(0x0)
+    yield
+
+    yield dut.stwd_hit_i.eq(0x2)
+    yield
+
+
 def test_mem_fus():
     dut = MemFunctionUnits(4)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_mem_fus.il", "w") as f:
         f.write(vl)
 
+    run_simulation(dut, mem_sim(dut),
+                        vcd_name='test_mem_fus.vcd')
+
 
 if __name__ == '__main__':
     test_mem_fus()