From: Luke Kenneth Casson Leighton Date: Sat, 26 Jun 2021 12:37:25 +0000 (+0100) Subject: use If Elif in power_decoder conditions, a lot easier than switch/case X-Git-Tag: xlen-bcd~372 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=10fa67c0027f649a9af84cf863f3b8afea79ba19;p=openpower-isa.git use If Elif in power_decoder conditions, a lot easier than switch/case --- diff --git a/openpower/isatables/svldst_minor_58.csv b/openpower/isatables/svldst_minor_58.csv deleted file mode 100644 index 45355142..00000000 --- a/openpower/isatables/svldst_minor_58.csv +++ /dev/null @@ -1,4 +0,0 @@ -opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS -0,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ld,SVDS, -1,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldu,SVDS, -2,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwa,SVDS, diff --git a/openpower/isatables/svldst_minor_58.csv.disable b/openpower/isatables/svldst_minor_58.csv.disable new file mode 100644 index 00000000..45355142 --- /dev/null +++ b/openpower/isatables/svldst_minor_58.csv.disable @@ -0,0 +1,4 @@ +opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS +0,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ld,SVDS, +1,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldu,SVDS, +2,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVDS,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,1,lwa,SVDS, diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py index c5c98133..e3b2e932 100644 --- a/src/openpower/decoder/power_decoder.py +++ b/src/openpower/decoder/power_decoder.py @@ -88,8 +88,8 @@ Top Level: import gc from collections import namedtuple, OrderedDict -from nmigen import Module, Elaboratable, Signal, Cat, Mux -from nmigen.cli import rtlil +from nmigen import Module, Elaboratable, Signal, Cat, Mux, Const +from nmigen.cli import rtlil, verilog from openpower.decoder.power_enums import (Function, Form, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, SVEXTRA, SVEtype, SVPtype, # Simple-V @@ -323,8 +323,7 @@ class PowerDecoder(Elaboratable): row_subset=None, conditions=None): if conditions is None: # XXX conditions = {} - conditions = {'SVP64BREV': 0, - '~SVP64BREV': 1, + conditions = {'SVP64BREV': Const(0, 1), } self.actually_does_something = False self.pname = name @@ -351,13 +350,6 @@ class PowerDecoder(Elaboratable): self.ccases = {} self.ckeys = list(conditions.keys()) self.ckeys.sort() - cswitch = [] - for i, ckey in enumerate(self.ckeys): - case = ['-'] * len(self.ckeys) - case[i] = '1' - self.ccases[ckey] = ''.join(case) - cswitch.append(conditions[ckey]) - self.cswitch = cswitch def find_conditions(self, opcodes): # look for conditions, create dictionary entries for them @@ -368,7 +360,9 @@ class PowerDecoder(Elaboratable): opcode = row['opcode'] if condition: # check it's expected - assert condition in self.conditions, \ + assert (condition in self.conditions or + (condition[0] == '~' and + condition[1:] in self.conditions)), \ "condition %s not in %s" % (condition, str(conditions)) if opcode not in rows: rows[opcode] = {} @@ -556,9 +550,14 @@ class PowerDecoder(Elaboratable): entries for a given opcode match. here we discern them. """ comb = m.d.comb - with m.Switch(Cat(*self.cswitch)): - for ckey, eqs in cases.items(): - with m.Case(self.ccases[ckey]): + cswitch = [] + ccases = [] + for casekey, eqs in cases.items(): + if casekey.startswith('~'): + with m.If(~self.conditions[casekey[1:]]): + comb += eqs + else: + with m.If(self.conditions[casekey]): comb += eqs def ports(self): @@ -772,11 +771,10 @@ if __name__ == '__main__': return row['unit'] == 'LDST' conditions = {'SVP64BREV': Signal(name="svp64brev", reset_less=True), - '~SVP64BREV': Signal(name="svp64brevN", reset_less=True) } pdecode = create_pdecode(name="rowsub", col_subset={'opcode', 'function_unit', - 'form'}, + 'in2_sel', 'in3_sel'}, row_subset=rowsubsetfn, include_fp=True, conditions=conditions) @@ -784,6 +782,12 @@ if __name__ == '__main__': with open("row_subset_decoder.il", "w") as f: f.write(vl) + vl = verilog.convert(pdecode, ports=pdecode.ports()) + with open("row_subset_decoder.v", "w") as f: + f.write(vl) + + exit(0) + # col subset pdecode = create_pdecode(name="fusubset", col_subset={'function_unit'}) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 6ee8f821..f4a955d5 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -779,10 +779,10 @@ class PowerDecodeSubset(Elaboratable): # amongst other things if svp64_en: conditions = {'SVP64BREV': self.use_svp64_ldst_dec, - '~SVP64BREV': ~self.use_svp64_ldst_dec } else: - conditions = None + conditions = {'SVP64BREV': Const(0, 1), + } # only needed for "main" PowerDecode2 if not self.final: