From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 10:26:57 +0000 (+0000) Subject: update libresoc.v, c4m-jtag fsm was renamed X-Git-Tag: LS180_RC3~115 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1100bf068ad299f4f8ae61ff792ba48e2f99e840;p=soclayout.git update libresoc.v, c4m-jtag fsm was renamed --- diff --git a/experiments9/non_generated/libresoc.v b/experiments9/non_generated/libresoc.v index 6278c77..ccb3448 100644 --- a/experiments9/non_generated/libresoc.v +++ b/experiments9/non_generated/libresoc.v @@ -1,4 +1,4 @@ -/* Generated by Yosys 0.9+4008 (git sha1 049e3abf, ccache clang 9.0.1-12 -O0 -O3 -DNDEBUG -fPIC) */ +/* Generated by Yosys 0.9+4052 (git sha1 a58571d0, clang 9.0.1-12 -fPIC -Os) */ (* \nmigen.hierarchy = "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" *) (* generator = "nMigen" *) @@ -6387,7 +6387,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - CR_dec31_dec_sub15_function_unit = 14'h0000; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -6490,7 +6490,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i end always @* begin if (\initial ) begin end - CR_dec31_dec_sub15_internal_op = 7'h00; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -6593,7 +6593,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i end always @* begin if (\initial ) begin end - CR_dec31_dec_sub15_cr_in = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -6696,7 +6696,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i end always @* begin if (\initial ) begin end - CR_dec31_dec_sub15_cr_out = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -6799,7 +6799,7 @@ module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_i end always @* begin if (\initial ) begin end - CR_dec31_dec_sub15_rc_sel = 2'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -20715,494 +20715,6 @@ module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub1 assign opcode_switch = opcode_in[10:6]; endmodule -(* \nmigen.hierarchy = "test_issuer.ti.jtag._fsm" *) -(* generator = "nMigen" *) -module _fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, negjtag_clk, TAP_bus__tck, TAP_bus__tms, isdr); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) - wire \$11 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) - wire \$13 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) - wire \$15 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) - wire \$17 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) - wire \$19 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) - wire \$21 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) - wire \$23 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) - wire \$25 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) - wire \$27 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) - wire \$29 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) - wire \$3 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) - wire \$31 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) - wire \$5 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) - wire \$7 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) - wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) - input TAP_bus__tck; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) - input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) - output capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) - reg [3:0] fsm_state = 4'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) - reg [3:0] \fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) - output isdr; - reg isdr = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) - reg \isdr$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) - output isir; - reg isir = 1'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) - reg \isir$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" *) - wire local_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) - output negjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) - output negjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) - output posjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) - output posjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" *) - wire rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) - output shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) - output update; - assign \$9 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0; - assign \$11 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0; - assign \$13 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) 1'h0; - assign \$15 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) 1'h1; - assign \$17 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0; - assign \$1 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *) 1'h0; - assign \$19 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0; - assign \$21 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) 1'h0; - assign \$23 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) 1'h1; - assign \$25 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) 1'h0; - assign \$27 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) 1'h1; - assign \$29 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) 1'h0; - assign \$31 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) 1'h0; - assign \$3 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) 2'h3; - assign \$5 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) 3'h5; - assign \$7 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) 4'h8; - always @(posedge local_clk) - fsm_state <= \fsm_state$next ; - always @(posedge local_clk) - isdr <= \isdr$next ; - always @(posedge local_clk) - isir <= \isir$next ; - always @* begin - if (\initial ) begin end - \isdr$next = isdr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) - casez (fsm_state) - /* \nmigen.decoding = "TestLogicReset/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ - 4'h0: - \isdr$next = 1'h0; - /* \nmigen.decoding = "RunTestIdle/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ - 4'h1: - \isdr$next = 1'h0; - /* \nmigen.decoding = "SelectDRScan/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ - 4'h2: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) - casez (\$11 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ - 1'h1: - \isdr$next = 1'h1; - endcase - /* \nmigen.decoding = "SelectIRScan/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ - 4'h4: - /* empty */; - /* \nmigen.decoding = "CaptureState/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ - 4'h3: - /* empty */; - /* \nmigen.decoding = "ShiftState/5" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ - 4'h5: - /* empty */; - /* \nmigen.decoding = "Exit1/6" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ - 4'h6: - /* empty */; - /* \nmigen.decoding = "Pause/7" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ - 4'h7: - /* empty */; - /* \nmigen.decoding = "Exit2/9" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ - 4'h9: - /* empty */; - /* \nmigen.decoding = "UpdateState/8" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ - 4'h8: - \isdr$next = 1'h0; - endcase - end - always @* begin - if (\initial ) begin end - \fsm_state$next = fsm_state; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) - casez (fsm_state) - /* \nmigen.decoding = "TestLogicReset/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ - 4'h0: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) - casez (\$13 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" */ - 1'h1: - \fsm_state$next = 4'h1; - endcase - /* \nmigen.decoding = "RunTestIdle/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ - 4'h1: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) - casez (\$15 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" */ - 1'h1: - \fsm_state$next = 4'h2; - endcase - /* \nmigen.decoding = "SelectDRScan/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ - 4'h2: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) - casez (\$17 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ - 1'h1: - \fsm_state$next = 4'h3; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:73" */ - default: - \fsm_state$next = 4'h4; - endcase - /* \nmigen.decoding = "SelectIRScan/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ - 4'h4: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) - casez (\$19 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ - 1'h1: - \fsm_state$next = 4'h3; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:79" */ - default: - \fsm_state$next = 4'h0; - endcase - /* \nmigen.decoding = "CaptureState/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ - 4'h3: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) - casez (\$21 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ - 1'h1: - \fsm_state$next = 4'h5; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:84" */ - default: - \fsm_state$next = 4'h6; - endcase - /* \nmigen.decoding = "ShiftState/5" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ - 4'h5: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) - casez (\$23 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ - 1'h1: - \fsm_state$next = 4'h6; - endcase - /* \nmigen.decoding = "Exit1/6" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ - 4'h6: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) - casez (\$25 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ - 1'h1: - \fsm_state$next = 4'h7; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:92" */ - default: - \fsm_state$next = 4'h8; - endcase - /* \nmigen.decoding = "Pause/7" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ - 4'h7: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) - casez (\$27 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ - 1'h1: - \fsm_state$next = 4'h9; - endcase - /* \nmigen.decoding = "Exit2/9" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ - 4'h9: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) - casez (\$29 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ - 1'h1: - \fsm_state$next = 4'h5; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:100" */ - default: - \fsm_state$next = 4'h8; - endcase - /* \nmigen.decoding = "UpdateState/8" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ - 4'h8: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) - casez (\$31 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" */ - 1'h1: - \fsm_state$next = 4'h1; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:109" */ - default: - \fsm_state$next = 4'h2; - endcase - endcase - end - always @* begin - if (\initial ) begin end - \isir$next = isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) - casez (fsm_state) - /* \nmigen.decoding = "TestLogicReset/0" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ - 4'h0: - \isir$next = 1'h0; - /* \nmigen.decoding = "RunTestIdle/1" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ - 4'h1: - \isir$next = 1'h0; - /* \nmigen.decoding = "SelectDRScan/2" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ - 4'h2: - /* empty */; - /* \nmigen.decoding = "SelectIRScan/4" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ - 4'h4: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) - casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ - 1'h1: - \isir$next = 1'h1; - endcase - /* \nmigen.decoding = "CaptureState/3" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ - 4'h3: - /* empty */; - /* \nmigen.decoding = "ShiftState/5" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ - 4'h5: - /* empty */; - /* \nmigen.decoding = "Exit1/6" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ - 4'h6: - /* empty */; - /* \nmigen.decoding = "Pause/7" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ - 4'h7: - /* empty */; - /* \nmigen.decoding = "Exit2/9" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ - 4'h9: - /* empty */; - /* \nmigen.decoding = "UpdateState/8" */ - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ - 4'h8: - \isir$next = 1'h0; - endcase - end - assign update = \$7 ; - assign shift = \$5 ; - assign capture = \$3 ; - assign rst = \$1 ; - assign local_clk = TAP_bus__tck; - assign negjtag_rst = rst; - assign negjtag_clk = TAP_bus__tck; - assign posjtag_rst = rst; - assign posjtag_clk = TAP_bus__tck; -endmodule - -(* \nmigen.hierarchy = "test_issuer.ti.jtag._idblock" *) -(* generator = "nMigen" *) -module _idblock(id_bypass, capture, shift, update, TAP_bus__tdi, TAP_id_tdo, posjtag_rst, posjtag_clk, select_id); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) - wire \$3 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *) - wire \$5 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) - input TAP_bus__tdi; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *) - reg [31:0] TAP_id_sr = 32'd0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *) - reg [31:0] \TAP_id_sr$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *) - output TAP_id_tdo; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" *) - wire _bypass; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" *) - wire _capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *) - wire _shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" *) - wire _tdi; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" *) - wire _update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) - input capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *) - input id_bypass; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) - input posjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) - input posjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) - input select_id; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) - input shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) - input update; - assign \$1 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) capture; - assign \$3 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) shift; - assign \$5 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *) update; - always @(posedge posjtag_clk) - TAP_id_sr <= \TAP_id_sr$next ; - always @* begin - if (\initial ) begin end - \TAP_id_sr$next = TAP_id_sr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" *) - casez ({ _shift, _capture }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" */ - 2'b?1: - \TAP_id_sr$next = 32'd6399; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:256" */ - 2'b1?: - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" *) - casez (_bypass) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" */ - 1'h1: - \TAP_id_sr$next [0] = _tdi; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:259" */ - default: - \TAP_id_sr$next = { _tdi, TAP_id_sr[31:1] }; - endcase - endcase - end - assign TAP_id_tdo = TAP_id_sr[0]; - assign _bypass = id_bypass; - assign _update = \$5 ; - assign _shift = \$3 ; - assign _capture = \$1 ; - assign _tdi = TAP_bus__tdi; -endmodule - -(* \nmigen.hierarchy = "test_issuer.ti.jtag._irblock" *) -(* generator = "nMigen" *) -module _irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, posjtag_clk, ir); - reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) - wire \$1 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) - wire \$11 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) - wire \$3 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) - wire \$5 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) - wire \$7 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) - wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) - input TAP_bus__tdi; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) - input capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) - output [3:0] ir; - reg [3:0] ir = 4'h1; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) - reg [3:0] \ir$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) - input isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) - input posjtag_clk; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) - input posjtag_rst; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) - input shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *) - reg [3:0] shift_ir = 4'h0; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *) - reg [3:0] \shift_ir$next ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *) - output tdo; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) - input update; - assign \$9 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift; - assign \$11 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update; - assign \$1 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture; - assign \$3 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift; - assign \$5 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update; - assign \$7 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture; - always @(posedge posjtag_clk) - ir <= \ir$next ; - always @(posedge posjtag_clk) - shift_ir <= \shift_ir$next ; - always @* begin - if (\initial ) begin end - \shift_ir$next = shift_ir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *) - casez ({ \$5 , \$3 , \$1 }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" */ - 3'b??1: - \shift_ir$next = ir; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ - 3'b?1?: - \shift_ir$next = { TAP_bus__tdi, shift_ir[3:1] }; - endcase - end - always @* begin - if (\initial ) begin end - \ir$next = ir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *) - casez ({ \$11 , \$9 , \$7 }) - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" */ - 3'b??1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ - 3'b?1?: - /* empty */; - /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:145" */ - 3'b1??: - \ir$next = shift_ir; - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) - casez (posjtag_rst) - 1'h1: - \ir$next = 4'h1; - endcase - end - assign tdo = ir[0]; -endmodule - (* \nmigen.hierarchy = "test_issuer.ti.core.fus.ldst0.adr_l" *) (* generator = "nMigen" *) module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); @@ -21223,9 +20735,9 @@ module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_adr; @@ -21254,7 +20766,7 @@ module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -21285,9 +20797,9 @@ module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_a wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_addr_acked; @@ -21316,7 +20828,7 @@ module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_a always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -21695,9 +21207,9 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output cr_a_ok; @@ -22274,7 +21786,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -22283,7 +21795,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -22292,7 +21804,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -22301,7 +21813,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -22310,7 +21822,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -22319,7 +21831,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -22328,7 +21840,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 4'h0; @@ -22337,7 +21849,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 4'hf; @@ -22346,7 +21858,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 5'h00; @@ -22355,7 +21867,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 5'h1f; @@ -22387,7 +21899,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \alu_alu0_alu_op__insn$next , \alu_alu0_alu_op__data_len$next , \alu_alu0_alu_op__is_signed$next , \alu_alu0_alu_op__is_32bit$next , \alu_alu0_alu_op__output_carry$next , \alu_alu0_alu_op__input_carry$next , \alu_alu0_alu_op__write_cr0$next , \alu_alu0_alu_op__invert_out$next , \alu_alu0_alu_op__zero_a$next , \alu_alu0_alu_op__invert_in$next , \alu_alu0_alu_op__oe__ok$next , \alu_alu0_alu_op__oe__oe$next , \alu_alu0_alu_op__rc__ok$next , \alu_alu0_alu_op__rc__rc$next , \alu_alu0_alu_op__imm_data__ok$next , \alu_alu0_alu_op__imm_data__data$next , \alu_alu0_alu_op__fn_unit$next , \alu_alu0_alu_op__insn_type$next } = { oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -22416,7 +21928,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -22438,7 +21950,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -22460,7 +21972,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__xer_ca_ok$next = 1'h0; @@ -22482,7 +21994,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r3__xer_ov_ok$next , \data_r3__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r3__xer_ov_ok$next = 1'h0; @@ -22504,7 +22016,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, 1'h1: { \data_r4__xer_so_ok$next , \data_r4__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r4__xer_so_ok$next = 1'h0; @@ -22553,7 +22065,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$99 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -22562,7 +22074,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$101 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -22621,7 +22133,7 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 5'h00; @@ -22925,9 +22437,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ input alu_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \alu_op__zero_a$63 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -23959,9 +23471,9 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ input br_op__lk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \br_op__lk$21 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_a; @@ -24298,9 +23810,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *) (* generator = "nMigen" *) module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -24817,9 +24329,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *) (* generator = "nMigen" *) module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -26303,9 +25815,9 @@ module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26334,7 +25846,7 @@ module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26365,9 +25877,9 @@ module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26396,7 +25908,7 @@ module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26427,9 +25939,9 @@ module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26458,7 +25970,7 @@ module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26489,9 +26001,9 @@ module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26520,7 +26032,7 @@ module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26551,9 +26063,9 @@ module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26582,7 +26094,7 @@ module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26613,9 +26125,9 @@ module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26644,7 +26156,7 @@ module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26675,9 +26187,9 @@ module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26706,7 +26218,7 @@ module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26737,9 +26249,9 @@ module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26768,7 +26280,7 @@ module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26799,9 +26311,9 @@ module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26830,7 +26342,7 @@ module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26861,9 +26373,9 @@ module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -26892,7 +26404,7 @@ module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -26906,9 +26418,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *) (* generator = "nMigen" *) module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -27923,9 +27435,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *) (* generator = "nMigen" *) module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -29144,9 +28656,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *) (* generator = "nMigen" *) module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -30181,9 +29693,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *) (* generator = "nMigen" *) module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [63:0] fast1; @@ -30743,9 +30255,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *) (* generator = "nMigen" *) module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, o, fast1, fast2, nia, msr, ra, rb, \fast1$1 , \fast2$2 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [63:0] fast1; @@ -31637,9 +31149,9 @@ module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31668,7 +31180,7 @@ module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31699,9 +31211,9 @@ module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31730,7 +31242,7 @@ module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31761,9 +31273,9 @@ module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31792,7 +31304,7 @@ module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31823,9 +31335,9 @@ module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31854,7 +31366,7 @@ module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31885,9 +31397,9 @@ module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31916,7 +31428,7 @@ module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -31947,9 +31459,9 @@ module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -31978,7 +31490,7 @@ module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -32009,9 +31521,9 @@ module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -32040,7 +31552,7 @@ module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -32071,9 +31583,9 @@ module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -32102,7 +31614,7 @@ module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -32133,9 +31645,9 @@ module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -32164,7 +31676,7 @@ module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -32362,6 +31874,7 @@ module bpermd(rb, ra, rs); casez (\$1 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_0) 8'h00: @@ -32498,6 +32011,7 @@ module bpermd(rb, ra, rs); casez (\$3 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_1) 8'h00: @@ -32634,6 +32148,7 @@ module bpermd(rb, ra, rs); casez (\$5 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_2) 8'h00: @@ -32770,6 +32285,7 @@ module bpermd(rb, ra, rs); casez (\$7 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_3) 8'h00: @@ -32906,6 +32422,7 @@ module bpermd(rb, ra, rs); casez (\$9 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_4) 8'h00: @@ -33042,6 +32559,7 @@ module bpermd(rb, ra, rs); casez (\$11 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_5) 8'h00: @@ -33178,6 +32696,7 @@ module bpermd(rb, ra, rs); casez (\$13 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_6) 8'h00: @@ -33314,6 +32833,7 @@ module bpermd(rb, ra, rs); casez (\$15 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *) casez (idx_7) 8'h00: @@ -33821,9 +33341,9 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -34285,7 +33805,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -34294,7 +33814,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -34303,7 +33823,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -34312,7 +33832,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -34321,7 +33841,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -34330,7 +33850,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -34339,7 +33859,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -34348,7 +33868,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -34357,7 +33877,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -34366,7 +33886,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -34388,7 +33908,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \alu_branch0_br_op__is_32bit$next , \alu_branch0_br_op__lk$next , \alu_branch0_br_op__imm_data__ok$next , \alu_branch0_br_op__imm_data__data$next , \alu_branch0_br_op__insn$next , \alu_branch0_br_op__fn_unit$next , \alu_branch0_br_op__insn_type$next , \alu_branch0_br_op__cia$next } = { oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -34413,7 +33933,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r0__fast1_ok$next , \data_r0__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__fast1_ok$next = 1'h0; @@ -34435,7 +33955,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r1__fast2_ok$next , \data_r1__fast2$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__fast2_ok$next = 1'h0; @@ -34457,7 +33977,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t 1'h1: { \data_r2__nia_ok$next , \data_r2__nia$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__nia_ok$next = 1'h0; @@ -34496,7 +34016,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$87 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -34505,7 +34025,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -34544,7 +34064,7 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -34602,9 +34122,9 @@ module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_busy; @@ -34633,7 +34153,7 @@ module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -35123,6 +34643,7 @@ module clz(lz, sig_in); assign \$97 = cnt_2_2[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair0) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35138,6 +34659,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair10) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35153,6 +34675,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair12) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35168,6 +34691,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair14) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35183,6 +34707,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair16) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35198,6 +34723,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair18) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35213,6 +34739,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair20) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35228,6 +34755,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair22) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35243,6 +34771,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair24) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35258,6 +34787,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair26) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35273,6 +34803,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair28) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35288,6 +34819,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair2) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35303,6 +34835,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair30) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35318,6 +34851,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair32) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35333,6 +34867,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair34) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35348,6 +34883,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair36) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35363,6 +34899,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair38) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35378,6 +34915,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair40) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35393,6 +34931,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair42) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35408,6 +34947,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair44) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35423,6 +34963,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair46) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35438,6 +34979,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair48) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35453,6 +34995,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair4) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35468,6 +35011,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair50) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35483,6 +35027,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair52) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35498,6 +35043,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair54) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35513,6 +35059,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair56) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35528,6 +35075,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair58) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35543,6 +35091,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair60) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35558,6 +35107,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair62) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35573,10 +35123,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$1 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$3 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35593,10 +35145,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$7 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$9 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35613,10 +35167,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$13 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$15 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35633,10 +35189,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$19 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$21 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35653,10 +35211,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$25 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$27 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35673,10 +35233,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$31 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$33 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35693,6 +35255,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair6) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -35708,10 +35271,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$37 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$39 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35728,10 +35293,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$43 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$45 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35748,10 +35315,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$49 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$51 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35768,10 +35337,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$55 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$57 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35788,10 +35359,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$61 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$63 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35808,10 +35381,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$67 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$69 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35828,10 +35403,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$73 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$75 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35848,10 +35425,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$79 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$81 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35868,10 +35447,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$85 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$87 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35888,10 +35469,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$91 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$93 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35908,10 +35491,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$97 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$99 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35928,10 +35513,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$103 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$105 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35948,10 +35535,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$109 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$111 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35968,10 +35557,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$115 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$117 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -35988,10 +35579,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$121 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$123 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36008,10 +35601,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$127 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$129 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36028,10 +35623,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$133 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$135 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36048,10 +35645,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$139 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$141 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36068,10 +35667,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$145 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$147 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36088,10 +35689,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$151 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$153 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36108,6 +35711,7 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *) casez (pair8) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:34" */ @@ -36123,10 +35727,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$157 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$159 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36143,10 +35749,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$163 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$165 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36163,10 +35771,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$169 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$171 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36183,10 +35793,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$175 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$177 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36203,10 +35815,12 @@ module clz(lz, sig_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) casez (\$181 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) casez (\$183 ) /* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" */ @@ -36370,7 +35984,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire [63:0] \$1164 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [63:0] \$1166 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) wire [64:0] \$1168 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [64:0] \$1170 ; @@ -38108,9 +37722,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) output corebusy_o; reg corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) reg [1:0] counter = 2'h0; @@ -41370,7 +40984,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c wire \sv_a_nz$179 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *) wire \sv_a_nz$180 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) input wb_dcache_en; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] wen; @@ -41958,7 +41572,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c assign \$1162 = \fus_dest1_o$116 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1160 ; assign \$1164 = \$1158 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1162 ; assign \$1166 = \fus_dest1_o$119 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$120 ; - assign \$1168 = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) { ea_ok, fus_ea }; + assign \$1168 = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:258" *) { ea_ok, fus_ea }; assign \$1170 = \fus_dest1_o$121 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1168 ; assign \$1172 = \$1166 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1170 ; assign \$1174 = \$1164 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1172 ; @@ -43507,6 +43121,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43536,6 +43151,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43565,6 +43181,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43594,6 +43211,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43623,6 +43241,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43652,6 +43271,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43681,6 +43301,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43710,6 +43331,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43739,6 +43361,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43768,6 +43391,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43797,6 +43421,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43826,6 +43451,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43855,6 +43481,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43884,6 +43511,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43913,6 +43541,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43943,6 +43572,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -43973,6 +43603,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44003,6 +43634,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44032,6 +43664,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44061,6 +43694,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44090,6 +43724,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44119,6 +43754,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44148,6 +43784,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44177,6 +43814,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44206,6 +43844,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44235,6 +43874,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44264,6 +43904,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44293,6 +43934,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44322,6 +43964,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44351,6 +43994,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44380,6 +44024,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44409,6 +44054,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44439,6 +44085,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44469,6 +44116,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44499,6 +44147,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44528,6 +44177,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44557,6 +44207,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44586,6 +44237,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44615,6 +44267,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44644,6 +44297,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44673,6 +44327,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44702,6 +44357,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44731,6 +44387,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44761,6 +44418,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44791,6 +44449,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44821,6 +44480,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44850,6 +44510,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44879,6 +44540,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44908,6 +44570,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44937,6 +44600,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44966,6 +44630,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -44995,6 +44660,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45024,6 +44690,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45053,6 +44720,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45082,6 +44750,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45111,6 +44780,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45140,6 +44810,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45169,6 +44840,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45198,6 +44870,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45228,6 +44901,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45257,6 +44931,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45287,6 +44962,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45317,6 +44993,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45346,6 +45023,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45375,6 +45053,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45404,6 +45083,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45433,6 +45113,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45462,6 +45143,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45491,6 +45173,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45520,6 +45203,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45549,6 +45233,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45578,6 +45263,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -45603,7 +45289,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_alu0_0$next = rp_INT_rabc_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_alu0_0$next = 1'h0; @@ -45622,7 +45308,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_cr0_1$next = rp_INT_rabc_cr0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_cr0_1$next = 1'h0; @@ -45641,7 +45327,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_trap0_2$next = rp_INT_rabc_trap0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_trap0_2$next = 1'h0; @@ -45660,7 +45346,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_logical0_3$next = rp_INT_rabc_logical0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_logical0_3$next = 1'h0; @@ -45679,7 +45365,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_div0_4$next = rp_INT_rabc_div0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_div0_4$next = 1'h0; @@ -45698,7 +45384,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_mul0_5$next = rp_INT_rabc_mul0_5; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_mul0_5$next = 1'h0; @@ -45717,7 +45403,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_6$next = rp_INT_rabc_shiftrot0_6; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_6$next = 1'h0; @@ -45736,7 +45422,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_7$next = rp_INT_rabc_ldst0_7; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_7$next = 1'h0; @@ -45755,7 +45441,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_8$next = rp_INT_rabc_shiftrot0_8; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_8$next = 1'h0; @@ -45774,7 +45460,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_9$next = rp_INT_rabc_ldst0_9; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_9$next = 1'h0; @@ -45793,7 +45479,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_alu0_10$next = rp_INT_rabc_alu0_10; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_alu0_10$next = 1'h0; @@ -45812,7 +45498,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_cr0_11$next = rp_INT_rabc_cr0_11; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_cr0_11$next = 1'h0; @@ -45831,7 +45517,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_trap0_12$next = rp_INT_rabc_trap0_12; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_trap0_12$next = 1'h0; @@ -45850,7 +45536,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_logical0_13$next = rp_INT_rabc_logical0_13; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_logical0_13$next = 1'h0; @@ -45869,7 +45555,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_spr0_14$next = rp_INT_rabc_spr0_14; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_spr0_14$next = 1'h0; @@ -45888,7 +45574,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_div0_15$next = rp_INT_rabc_div0_15; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_div0_15$next = 1'h0; @@ -45907,7 +45593,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_mul0_16$next = rp_INT_rabc_mul0_16; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_mul0_16$next = 1'h0; @@ -45926,7 +45612,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_shiftrot0_17$next = rp_INT_rabc_shiftrot0_17; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_shiftrot0_17$next = 1'h0; @@ -45945,7 +45631,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_INT_rabc_ldst0_18$next = rp_INT_rabc_ldst0_18; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_INT_rabc_ldst0_18$next = 1'h0; @@ -45964,7 +45650,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_alu0_0$next = rp_XER_xer_so_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_alu0_0$next = 1'h0; @@ -45983,7 +45669,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_logical0_1$next = rp_XER_xer_so_logical0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_logical0_1$next = 1'h0; @@ -46002,7 +45688,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_spr0_2$next = rp_XER_xer_so_spr0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_spr0_2$next = 1'h0; @@ -46021,7 +45707,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_div0_3$next = rp_XER_xer_so_div0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_div0_3$next = 1'h0; @@ -46040,7 +45726,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_mul0_4$next = rp_XER_xer_so_mul0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_mul0_4$next = 1'h0; @@ -46059,7 +45745,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_so_shiftrot0_5$next = rp_XER_xer_so_shiftrot0_5; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_so_shiftrot0_5$next = 1'h0; @@ -46078,7 +45764,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_alu0_0$next = rp_XER_xer_ca_alu0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_alu0_0$next = 1'h0; @@ -46097,7 +45783,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_spr0_1$next = rp_XER_xer_ca_spr0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_spr0_1$next = 1'h0; @@ -46116,7 +45802,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ca_shiftrot0_2$next = rp_XER_xer_ca_shiftrot0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ca_shiftrot0_2$next = 1'h0; @@ -46135,7 +45821,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_XER_xer_ov_spr0_0$next = rp_XER_xer_ov_spr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_XER_xer_ov_spr0_0$next = 1'h0; @@ -46154,7 +45840,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_full_cr_cr0_0$next = rp_CR_full_cr_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_CR_full_cr_cr0_0$next = 1'h0; @@ -46173,7 +45859,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_a_cr0_0$next = rp_CR_cr_a_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_CR_cr_a_cr0_0$next = 1'h0; @@ -46192,7 +45878,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_a_branch0_1$next = rp_CR_cr_a_branch0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_CR_cr_a_branch0_1$next = 1'h0; @@ -46211,7 +45897,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_b_cr0_0$next = rp_CR_cr_b_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_CR_cr_b_cr0_0$next = 1'h0; @@ -46242,7 +45928,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c \counter$next = 2'h2; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \counter$next = 2'h0; @@ -46261,7 +45947,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_CR_cr_c_cr0_0$next = rp_CR_cr_c_cr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_CR_cr_c_cr0_0$next = 1'h0; @@ -46290,6 +45976,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46371,7 +46058,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_branch0_0$next = rp_FAST_fast1_branch0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_branch0_0$next = 1'h0; @@ -46402,7 +46089,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c \core_terminate_o$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \core_terminate_o$next = 1'h0; @@ -46411,7 +46098,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_trap0_1$next = rp_FAST_fast1_trap0_1; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_trap0_1$next = 1'h0; @@ -46430,7 +46117,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_spr0_2$next = rp_FAST_fast1_spr0_2; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_spr0_2$next = 1'h0; @@ -46453,6 +46140,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46478,7 +46166,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_branch0_3$next = rp_FAST_fast1_branch0_3; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_branch0_3$next = 1'h0; @@ -46497,7 +46185,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_FAST_fast1_trap0_4$next = rp_FAST_fast1_trap0_4; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_FAST_fast1_trap0_4$next = 1'h0; @@ -46520,6 +46208,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46545,7 +46234,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \dp_SPR_spr1_spr0_0$next = rp_SPR_spr1_spr0_0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dp_SPR_spr1_spr0_0$next = 1'h0; @@ -46569,6 +46258,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46594,7 +46284,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$next = wr_pick; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$next = 1'h0; @@ -46603,7 +46293,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$989$next = \wr_pick$986 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$989$next = 1'h0; @@ -46612,7 +46302,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1008$next = \wr_pick$1005 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1008$next = 1'h0; @@ -46626,6 +46316,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46651,7 +46342,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1029$next = \wr_pick$1026 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1029$next = 1'h0; @@ -46660,7 +46351,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1047$next = \wr_pick$1044 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1047$next = 1'h0; @@ -46669,7 +46360,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1069$next = \wr_pick$1066 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1069$next = 1'h0; @@ -46683,6 +46374,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46708,7 +46400,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1089$next = \wr_pick$1086 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1089$next = 1'h0; @@ -46717,7 +46409,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1109$next = \wr_pick$1106 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1109$next = 1'h0; @@ -46726,7 +46418,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1128$next = \wr_pick$1125 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1128$next = 1'h0; @@ -46739,6 +46431,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46764,7 +46457,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1146$next = \wr_pick$1143 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1146$next = 1'h0; @@ -46777,6 +46470,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46802,7 +46496,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1220$next = \wr_pick$1217 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1220$next = 1'h0; @@ -46815,6 +46509,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46840,7 +46535,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1248$next = \wr_pick$1245 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1248$next = 1'h0; @@ -46853,6 +46548,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46878,7 +46574,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1268$next = \wr_pick$1265 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1268$next = 1'h0; @@ -46887,7 +46583,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1288$next = \wr_pick$1285 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1288$next = 1'h0; @@ -46900,6 +46596,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46925,7 +46622,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1308$next = \wr_pick$1305 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1308$next = 1'h0; @@ -46934,7 +46631,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1328$next = \wr_pick$1325 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1328$next = 1'h0; @@ -46947,6 +46644,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -46972,7 +46670,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1348$next = \wr_pick$1345 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1348$next = 1'h0; @@ -46985,6 +46683,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47010,7 +46709,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1395$next = \wr_pick$1392 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1395$next = 1'h0; @@ -47023,6 +46722,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47048,7 +46748,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1411$next = \wr_pick$1408 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1411$next = 1'h0; @@ -47057,7 +46757,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1427$next = \wr_pick$1424 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1427$next = 1'h0; @@ -47070,6 +46770,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47095,7 +46796,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1461$next = \wr_pick$1458 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1461$next = 1'h0; @@ -47108,6 +46809,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47133,7 +46835,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1477$next = \wr_pick$1474 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1477$next = 1'h0; @@ -47142,7 +46844,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1493$next = \wr_pick$1490 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1493$next = 1'h0; @@ -47155,6 +46857,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47180,7 +46883,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1509$next = \wr_pick$1506 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1509$next = 1'h0; @@ -47193,6 +46896,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47218,7 +46922,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1545$next = \wr_pick$1542 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1545$next = 1'h0; @@ -47227,7 +46931,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1561$next = \wr_pick$1558 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1561$next = 1'h0; @@ -47240,6 +46944,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47265,7 +46970,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1577$next = \wr_pick$1574 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1577$next = 1'h0; @@ -47278,6 +46983,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47303,7 +47009,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1593$next = \wr_pick$1590 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1593$next = 1'h0; @@ -47312,7 +47018,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1635$next = \wr_pick$1632 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1635$next = 1'h0; @@ -47325,6 +47031,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47350,7 +47057,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1654$next = \wr_pick$1651 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1654$next = 1'h0; @@ -47363,6 +47070,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47388,7 +47096,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1670$next = \wr_pick$1667 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1670$next = 1'h0; @@ -47397,7 +47105,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1686$next = \wr_pick$1683 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1686$next = 1'h0; @@ -47410,6 +47118,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47435,7 +47144,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1702$next = \wr_pick$1699 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1702$next = 1'h0; @@ -47448,6 +47157,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47473,7 +47183,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1746$next = \wr_pick$1743 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1746$next = 1'h0; @@ -47486,6 +47196,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47511,7 +47222,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1762$next = \wr_pick$1759 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1762$next = 1'h0; @@ -47520,7 +47231,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1786$next = \wr_pick$1783 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1786$next = 1'h0; @@ -47533,6 +47244,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47558,7 +47270,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c always @* begin if (\initial ) begin end \wr_pick_dly$1806$next = \wr_pick$1803 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wr_pick_dly$1806$next = 1'h0; @@ -47571,6 +47283,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47601,6 +47314,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47630,6 +47344,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47659,6 +47374,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47688,6 +47404,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47717,6 +47434,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47746,6 +47464,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47775,6 +47494,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47804,6 +47524,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47833,6 +47554,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47862,6 +47584,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47891,6 +47614,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47920,6 +47644,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47949,6 +47674,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -47978,6 +47704,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48007,6 +47734,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48036,6 +47764,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48065,6 +47794,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48094,6 +47824,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48124,6 +47855,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48154,6 +47886,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48184,6 +47917,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48213,6 +47947,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48242,6 +47977,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48271,6 +48007,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48300,6 +48037,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48329,6 +48067,7 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c casez (ivalid_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *) casez (core_core_insn_type) /* \nmigen.decoding = "OP_ATTN/5" */ @@ -48968,9 +48707,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] data_i; @@ -49468,7 +49207,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$17$next = src2__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$17$next = 8'h00; @@ -49487,7 +49226,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$34$next = src3__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$34$next = 8'h00; @@ -49506,7 +49245,7 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$next = 8'h00; @@ -49837,9 +49576,9 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output cr_a_ok; @@ -50299,7 +50038,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -50308,7 +50047,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -50317,7 +50056,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -50326,7 +50065,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -50335,7 +50074,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -50344,7 +50083,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -50353,7 +50092,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 6'h00; @@ -50362,7 +50101,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 6'h3f; @@ -50371,7 +50110,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -50380,7 +50119,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -50414,7 +50153,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -50436,7 +50175,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r1__full_cr_ok$next , \data_r1__full_cr$next } = 33'h000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__full_cr_ok$next = 1'h0; @@ -50458,7 +50197,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope 1'h1: { \data_r2__cr_a_ok$next , \data_r2__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__cr_a_ok$next = 1'h0; @@ -50527,7 +50266,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -50536,7 +50275,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -50575,7 +50314,7 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -50628,9 +50367,9 @@ module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_cyc; @@ -50656,7 +50395,7 @@ module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -50721,7 +50460,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r wire \$27 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) wire \$29 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) wire [63:0] \$3 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) wire \$31 ; @@ -50799,7 +50538,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r wire \$97 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) wire \$99 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) input [6:0] core_dbg_core_dbg_dststep; @@ -50902,7 +50641,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r wire [63:0] log_dmi_data; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *) wire [31:0] log_write_addr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *) wire [63:0] stat_reg; @@ -50948,7 +50687,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r assign \$33 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1; assign \$35 = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$33 ; assign \$37 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data; - assign \$3 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) { core_dbg_core_dbg_maxvl, core_dbg_core_dbg_vl, core_dbg_core_dbg_srcstep, core_dbg_core_dbg_dststep, core_dbg_core_dbg_subvl, core_dbg_core_dbg_svstep }; + assign \$3 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { core_dbg_core_dbg_maxvl, core_dbg_core_dbg_vl, core_dbg_core_dbg_srcstep, core_dbg_core_dbg_dststep, core_dbg_core_dbg_subvl, core_dbg_core_dbg_svstep }; assign \$39 = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$37 ; assign \$41 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0; assign \$43 = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4; @@ -51005,6 +50744,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r do_step <= \do_step$next ; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *) casez (dmi_addr_i) /* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" */ @@ -51034,7 +50774,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r always @* begin if (\initial ) begin end \dmi_req_i_1$next = dmi_req_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi_req_i_1$next = 1'h0; @@ -51084,7 +50824,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 1'h1: \terminated$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \terminated$next = 1'h0; @@ -51128,7 +50868,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 1'h1: \stopping$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \stopping$next = 1'h0; @@ -51156,7 +50896,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \gspr_index$next = 7'h00; @@ -51190,7 +50930,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 2'b1?: \log_dmi_addr$next [1:0] = \$117 [1:0]; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \log_dmi_addr$next = 32'd0; @@ -51199,7 +50939,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r always @* begin if (\initial ) begin end \dmi_read_log_data_1$next = dmi_read_log_data; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi_read_log_data_1$next = 1'h0; @@ -51208,7 +50948,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r always @* begin if (\initial ) begin end \dmi_read_log_data$next = \$122 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi_read_log_data$next = 1'h0; @@ -51301,7 +51041,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \do_step$next = 1'h0; @@ -51331,7 +51071,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \do_reset$next = 1'h0; @@ -51361,7 +51101,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \do_icreset$next = 1'h0; @@ -51395,7 +51135,7 @@ module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_r 2'b1?: \do_dmi_log_rd$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \do_dmi_log_rd$next = 1'h0; @@ -78913,6 +78653,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r ); always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$83 , \$75 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -79011,10 +78752,12 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" *) casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, \dec2_exc_$signal }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" */ 5'b????1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" *) casez ({ \dec2_exc_$signal$13 , \dec2_exc_$signal$12 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" */ @@ -79031,6 +78774,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r end /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1259" */ 2'b1?: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" *) casez (\dec2_exc_$signal$14 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" */ @@ -79061,6 +78805,7 @@ module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, r endcase /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1265" */ default: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" *) casez (\dec2_exc_$signal$14 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" */ @@ -95237,7 +94982,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o wire [4:0] opcode_switch; always @* begin if (\initial ) begin end - dec31_dec_sub15_function_unit = 14'h0000; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -95340,7 +95085,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_cr_in = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -95443,7 +95188,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_cr_out = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -95546,7 +95291,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sv_in1 = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -95649,7 +95394,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sv_in2 = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -95752,7 +95497,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sv_in3 = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -95855,7 +95600,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sv_out = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -95958,7 +95703,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sv_out2 = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96061,7 +95806,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sv_cr_in = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96164,7 +95909,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sv_cr_out = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96267,7 +96012,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_ldst_len = 4'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96370,7 +96115,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_internal_op = 7'h00; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96473,7 +96218,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_upd = 2'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96576,7 +96321,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_rc_sel = 2'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96679,7 +96424,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_cry_in = 2'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96782,7 +96527,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_asmcode = 8'h00; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96885,7 +96630,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_inv_a = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -96988,7 +96733,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_inv_out = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97091,7 +96836,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_cry_out = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97194,7 +96939,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_br = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97297,7 +97042,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sgn_ext = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97400,7 +97145,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_rsrv = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97503,7 +97248,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_form = 5'h00; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97606,7 +97351,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_is_32b = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97709,7 +97454,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sgn = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97812,7 +97557,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_lk = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -97915,7 +97660,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_sgl_pipe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -98018,7 +97763,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_SV_Etype = 2'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -98121,7 +97866,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_SV_Ptype = 2'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -98224,7 +97969,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_in1_sel = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -98327,7 +98072,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_in2_sel = 4'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -98430,7 +98175,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_in3_sel = 2'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -98533,7 +98278,7 @@ module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_o end always @* begin if (\initial ) begin end - dec31_dec_sub15_out_sel = 3'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *) casez (opcode_switch) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" */ @@ -121213,6 +120958,7 @@ module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -121684,6 +121430,7 @@ module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRAN ); always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -122087,6 +121834,7 @@ module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in); end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -122660,6 +122408,7 @@ module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -123226,6 +122975,7 @@ module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_da end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -123812,6 +123562,7 @@ module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOG end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -124326,6 +124077,7 @@ module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -124871,6 +124623,7 @@ module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -125263,6 +125016,7 @@ module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) casez ({ \$48 , \$40 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" */ @@ -128906,6 +128660,7 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_fxm = 8'h00; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ @@ -128939,6 +128694,7 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok /* \nmigen.decoding = "WHOLE_REG/6" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" */ 3'h6: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) casez (\$7 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" */ @@ -128984,6 +128740,7 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end cr_fxm_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ @@ -129139,6 +128896,7 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end move_one = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ @@ -129178,6 +128936,7 @@ module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok always @* begin if (\initial ) begin end ppick_i = 8'h00; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *) casez (sel_in) /* \nmigen.decoding = "NONE/0" */ @@ -129558,14 +129317,17 @@ module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bit /* \nmigen.decoding = "WHOLE_REG/4" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:657" */ 3'h4: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) casez (\$3 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *) casez (move_one) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" *) casez (ppick_en_o) /* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" */ @@ -130378,6 +130140,7 @@ module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (ALU_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130399,6 +130162,7 @@ module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (ALU_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130515,6 +130279,7 @@ module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (CR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130536,6 +130301,7 @@ module \dec_oe$140 (CR_internal_op, CR_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (CR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130652,6 +130418,7 @@ module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (BRANCH_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130673,6 +130440,7 @@ module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (BRANCH_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130791,6 +130559,7 @@ module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (LOGICAL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130812,6 +130581,7 @@ module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (LOGICAL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130928,6 +130698,7 @@ module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (SPR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -130949,6 +130720,7 @@ module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (SPR_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131067,6 +130839,7 @@ module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (DIV_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131088,6 +130861,7 @@ module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (DIV_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131206,6 +130980,7 @@ module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (MUL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131227,6 +131002,7 @@ module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (MUL_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131345,6 +131121,7 @@ module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (SHIFT_ROT_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131366,6 +131143,7 @@ module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (SHIFT_ROT_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131484,6 +131262,7 @@ module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (LDST_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131505,6 +131284,7 @@ module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (LDST_internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131623,6 +131403,7 @@ module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); always @* begin if (\initial ) begin end oe = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -131644,6 +131425,7 @@ module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in); always @* begin if (\initial ) begin end oe_ok = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *) casez (internal_op) /* \nmigen.decoding = "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" */ @@ -132594,9 +132376,9 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output cr_a_ok; @@ -133141,7 +132923,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -133150,7 +132932,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -133159,7 +132941,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -133168,7 +132950,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -133177,7 +132959,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -133186,7 +132968,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -133195,7 +132977,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -133204,7 +132986,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -133213,7 +132995,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 4'h0; @@ -133222,7 +133004,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 4'hf; @@ -133254,7 +133036,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \alu_div0_logical_op__insn$next , \alu_div0_logical_op__data_len$next , \alu_div0_logical_op__is_signed$next , \alu_div0_logical_op__is_32bit$next , \alu_div0_logical_op__output_carry$next , \alu_div0_logical_op__write_cr0$next , \alu_div0_logical_op__invert_out$next , \alu_div0_logical_op__input_carry$next , \alu_div0_logical_op__zero_a$next , \alu_div0_logical_op__invert_in$next , \alu_div0_logical_op__oe__ok$next , \alu_div0_logical_op__oe__oe$next , \alu_div0_logical_op__rc__ok$next , \alu_div0_logical_op__rc__rc$next , \alu_div0_logical_op__imm_data__ok$next , \alu_div0_logical_op__imm_data__data$next , \alu_div0_logical_op__fn_unit$next , \alu_div0_logical_op__insn_type$next } = { oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -133283,7 +133065,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -133305,7 +133087,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -133327,7 +133109,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__xer_ov_ok$next = 1'h0; @@ -133349,7 +133131,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -133388,7 +133170,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$94 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -133397,7 +133179,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$96 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -133446,7 +133228,7 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 4'h0; @@ -133545,6 +133327,7 @@ module div_state_next(o_q_bits_known, i_q_bits_known, i_dividend_quotient, divis assign \$8 = i_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 7'h40; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" *) casez (next_quotient_bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" */ @@ -133557,6 +133340,7 @@ module div_state_next(o_q_bits_known, i_q_bits_known, i_dividend_quotient, divis end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" *) casez (\$8 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" */ @@ -133569,6 +133353,7 @@ module div_state_next(o_q_bits_known, i_q_bits_known, i_dividend_quotient, divis end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" *) casez (\$13 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" */ @@ -133836,9 +133621,9 @@ endmodule (* generator = "nMigen" *) module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] dest1__addr; @@ -133922,7 +133707,7 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -133941,7 +133726,7 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 always @* begin if (\initial ) begin end \ren_delay$8$next = issue__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$8$next = 1'h0; @@ -133967,12 +133752,342 @@ module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 assign memory_r_addr = src1__addr; endmodule +(* \nmigen.hierarchy = "test_issuer.ti.jtag.fsm" *) +(* generator = "nMigen" *) +module fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, negjtag_clk, TAP_bus__tck, TAP_bus__tms, isdr); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) + wire \$13 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) + wire \$15 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + wire \$17 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + wire \$19 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) + wire \$21 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) + wire \$23 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) + wire \$25 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) + wire \$27 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) + wire \$29 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) + wire \$31 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tck; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tms; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + output capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + reg [3:0] fsm_state = 4'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + reg [3:0] \fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) + output isdr; + reg isdr = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) + reg \isdr$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + output isir; + reg isir = 1'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + reg \isir$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" *) + wire local_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + output negjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) + output negjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + output posjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + output posjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" *) + wire rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + output shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + output update; + assign \$9 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0; + assign \$11 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0; + assign \$13 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) 1'h0; + assign \$15 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) 1'h1; + assign \$17 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0; + assign \$1 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *) 1'h0; + assign \$19 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0; + assign \$21 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) 1'h0; + assign \$23 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) 1'h1; + assign \$25 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) 1'h0; + assign \$27 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) 1'h1; + assign \$29 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) 1'h0; + assign \$31 = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) 1'h0; + assign \$3 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) 2'h3; + assign \$5 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) 3'h5; + assign \$7 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) 4'h8; + always @(posedge local_clk) + fsm_state <= \fsm_state$next ; + always @(posedge local_clk) + isdr <= \isdr$next ; + always @(posedge local_clk) + isir <= \isir$next ; + always @* begin + if (\initial ) begin end + \isdr$next = isdr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + casez (fsm_state) + /* \nmigen.decoding = "TestLogicReset/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ + 4'h0: + \isdr$next = 1'h0; + /* \nmigen.decoding = "RunTestIdle/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ + 4'h1: + \isdr$next = 1'h0; + /* \nmigen.decoding = "SelectDRScan/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ + 4'h2: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + casez (\$11 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ + 1'h1: + \isdr$next = 1'h1; + endcase + /* \nmigen.decoding = "SelectIRScan/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ + 4'h4: + /* empty */; + /* \nmigen.decoding = "CaptureState/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "ShiftState/5" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "Exit1/6" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "Pause/7" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "Exit2/9" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "UpdateState/8" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ + 4'h8: + \isdr$next = 1'h0; + endcase + end + always @* begin + if (\initial ) begin end + \fsm_state$next = fsm_state; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + casez (fsm_state) + /* \nmigen.decoding = "TestLogicReset/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ + 4'h0: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) + casez (\$13 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" */ + 1'h1: + \fsm_state$next = 4'h1; + endcase + /* \nmigen.decoding = "RunTestIdle/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ + 4'h1: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) + casez (\$15 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" */ + 1'h1: + \fsm_state$next = 4'h2; + endcase + /* \nmigen.decoding = "SelectDRScan/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ + 4'h2: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) + casez (\$17 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" */ + 1'h1: + \fsm_state$next = 4'h3; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:73" */ + default: + \fsm_state$next = 4'h4; + endcase + /* \nmigen.decoding = "SelectIRScan/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ + 4'h4: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + casez (\$19 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ + 1'h1: + \fsm_state$next = 4'h3; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:79" */ + default: + \fsm_state$next = 4'h0; + endcase + /* \nmigen.decoding = "CaptureState/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ + 4'h3: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) + casez (\$21 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" */ + 1'h1: + \fsm_state$next = 4'h5; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:84" */ + default: + \fsm_state$next = 4'h6; + endcase + /* \nmigen.decoding = "ShiftState/5" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ + 4'h5: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) + casez (\$23 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" */ + 1'h1: + \fsm_state$next = 4'h6; + endcase + /* \nmigen.decoding = "Exit1/6" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ + 4'h6: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) + casez (\$25 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" */ + 1'h1: + \fsm_state$next = 4'h7; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:92" */ + default: + \fsm_state$next = 4'h8; + endcase + /* \nmigen.decoding = "Pause/7" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ + 4'h7: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) + casez (\$27 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" */ + 1'h1: + \fsm_state$next = 4'h9; + endcase + /* \nmigen.decoding = "Exit2/9" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ + 4'h9: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) + casez (\$29 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" */ + 1'h1: + \fsm_state$next = 4'h5; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:100" */ + default: + \fsm_state$next = 4'h8; + endcase + /* \nmigen.decoding = "UpdateState/8" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ + 4'h8: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) + casez (\$31 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" */ + 1'h1: + \fsm_state$next = 4'h1; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:109" */ + default: + \fsm_state$next = 4'h2; + endcase + endcase + end + always @* begin + if (\initial ) begin end + \isir$next = isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *) + casez (fsm_state) + /* \nmigen.decoding = "TestLogicReset/0" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" */ + 4'h0: + \isir$next = 1'h0; + /* \nmigen.decoding = "RunTestIdle/1" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:61" */ + 4'h1: + \isir$next = 1'h0; + /* \nmigen.decoding = "SelectDRScan/2" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:69" */ + 4'h2: + /* empty */; + /* \nmigen.decoding = "SelectIRScan/4" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:75" */ + 4'h4: + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) + casez (\$9 ) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" */ + 1'h1: + \isir$next = 1'h1; + endcase + /* \nmigen.decoding = "CaptureState/3" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:81" */ + 4'h3: + /* empty */; + /* \nmigen.decoding = "ShiftState/5" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:86" */ + 4'h5: + /* empty */; + /* \nmigen.decoding = "Exit1/6" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:89" */ + 4'h6: + /* empty */; + /* \nmigen.decoding = "Pause/7" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:94" */ + 4'h7: + /* empty */; + /* \nmigen.decoding = "Exit2/9" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:97" */ + 4'h9: + /* empty */; + /* \nmigen.decoding = "UpdateState/8" */ + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:102" */ + 4'h8: + \isir$next = 1'h0; + endcase + end + assign update = \$7 ; + assign shift = \$5 ; + assign capture = \$3 ; + assign rst = \$1 ; + assign local_clk = TAP_bus__tck; + assign negjtag_rst = rst; + assign negjtag_clk = TAP_bus__tck; + assign posjtag_rst = rst; + assign posjtag_clk = TAP_bus__tck; +endmodule + (* \nmigen.hierarchy = "test_issuer.ti.core.fus" *) (* generator = "nMigen" *) module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src2_i$79 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$80 , \cu_wr__rel_o$81 , \cu_wr__go_i$82 , \o_ok$83 , \cu_wr__rel_o$84 , \cu_wr__go_i$85 , \o_ok$86 , \cu_wr__rel_o$87 , \cu_wr__go_i$88 , \o_ok$89 , \cu_wr__rel_o$90 , \cu_wr__go_i$91 , \o_ok$92 , \cu_wr__rel_o$93 , \cu_wr__go_i$94 , \o_ok$95 , \cu_wr__rel_o$96 , \cu_wr__go_i$97 , \o_ok$98 , \cu_wr__rel_o$99 , \cu_wr__go_i$100 , \cu_wr__rel_o$101 , \cu_wr__go_i$102 , dest1_o, \dest1_o$103 , \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$110 , \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \dest2_o$115 , dest3_o, \dest2_o$116 , \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , xer_ca_ok, \xer_ca_ok$120 , \xer_ca_ok$121 , \dest3_o$122 , dest6_o, \dest3_o$123 , xer_ov_ok, \xer_ov_ok$124 , \xer_ov_ok$125 , \xer_ov_ok$126 , dest4_o, dest5_o, \dest3_o$127 , \dest3_o$128 , xer_so_ok, \xer_so_ok$129 , \xer_so_ok$130 , \xer_so_ok$131 , \dest5_o$132 , \dest4_o$133 , \dest4_o$134 , \dest4_o$135 , fast1_ok, \cu_wr__rel_o$136 , \cu_wr__go_i$137 , \fast1_ok$138 , \fast1_ok$139 , fast2_ok, \fast2_ok$140 , \dest1_o$141 , \dest2_o$142 , \dest3_o$143 , \dest2_o$144 , \dest3_o$145 , nia_ok, \nia_ok$146 , \dest3_o$147 , \dest4_o$148 , msr_ok, \dest5_o$149 , spr1_ok, \dest2_o$150 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$151 , \ldst_port0_exc_$signal$152 , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output cr_a_ok; @@ -135921,6 +136036,83 @@ module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, o ); endmodule +(* \nmigen.hierarchy = "test_issuer.ti.jtag.idblock" *) +(* generator = "nMigen" *) +module idblock(id_bypass, capture, shift, update, TAP_bus__tdi, TAP_id_tdo, posjtag_rst, posjtag_clk, select_id); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tdi; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *) + reg [31:0] TAP_id_sr = 32'd0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *) + reg [31:0] \TAP_id_sr$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *) + output TAP_id_tdo; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" *) + wire _bypass; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" *) + wire _capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *) + wire _shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" *) + wire _tdi; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" *) + wire _update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + input capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *) + input id_bypass; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + input posjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + input posjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) + input select_id; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + input shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + input update; + assign \$1 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) capture; + assign \$3 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) shift; + assign \$5 = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *) update; + always @(posedge posjtag_clk) + TAP_id_sr <= \TAP_id_sr$next ; + always @* begin + if (\initial ) begin end + \TAP_id_sr$next = TAP_id_sr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" *) + casez ({ _shift, _capture }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" */ + 2'b?1: + \TAP_id_sr$next = 32'd6399; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:256" */ + 2'b1?: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" *) + casez (_bypass) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" */ + 1'h1: + \TAP_id_sr$next [0] = _tdi; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:259" */ + default: + \TAP_id_sr$next = { _tdi, TAP_id_sr[31:1] }; + endcase + endcase + end + assign TAP_id_tdo = TAP_id_sr[0]; + assign _bypass = id_bypass; + assign _update = \$5 ; + assign _shift = \$3 ; + assign _capture = \$1 ; + assign _tdi = TAP_bus__tdi; +endmodule + (* \nmigen.hierarchy = "test_issuer.ti.core.l0.l0.idx_l" *) (* generator = "nMigen" *) module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); @@ -135941,9 +136133,9 @@ module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_idx_l; @@ -135972,7 +136164,7 @@ module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -136047,7 +136239,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en wire a_stall_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *) input a_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *) reg [44:0] f_badaddr_o = 45'h000000000000; @@ -136097,9 +136289,9 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en reg [63:0] ibus_rdata = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *) reg [63:0] \ibus_rdata$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) input wb_icache_en; assign \$9 = \$5 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$7 ; assign \$11 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i; @@ -136163,7 +136355,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__cyc$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \ibus__cyc$next = 1'h0; @@ -136191,7 +136383,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__stb$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \ibus__stb$next = 1'h0; @@ -136219,7 +136411,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__sel$next = 8'hff; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \ibus__sel$next = 8'h00; @@ -136244,7 +136436,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \ibus_rdata$next = 64'h0000000000000000; @@ -136267,7 +136459,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \ibus__adr$next = a_pc_i[47:3]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \ibus__adr$next = 45'h000000000000; @@ -136290,7 +136482,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \f_fetch_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \f_fetch_err_o$next = 1'h0; @@ -136310,7 +136502,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en \f_badaddr_o$next = ibus__adr; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \f_badaddr_o$next = 45'h000000000000; @@ -136333,6 +136525,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en casez (wb_icache_en) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" *) casez (f_fetch_err_o) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" */ @@ -136351,6 +136544,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en casez (wb_icache_en) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" *) casez (f_fetch_err_o) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" */ @@ -136660,6 +136854,7 @@ module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_o assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *) casez (alu_op__invert_in) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ @@ -136991,6 +137186,7 @@ module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_o assign \$24 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *) casez (sr_op__invert_in) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ @@ -137318,6 +137514,7 @@ module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_da assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" *) rb; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" *) casez (logical_op__invert_in) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" */ @@ -137625,6 +137822,7 @@ module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_da assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *) casez (logical_op__invert_in) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" */ @@ -137907,9 +138105,9 @@ endmodule (* generator = "nMigen" *) module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] dest1__addr; @@ -138004,7 +138202,7 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end \ren_delay$next = dmi__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -138023,7 +138221,7 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ always @* begin if (\initial ) begin end \ren_delay$4$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$4$next = 1'h0; @@ -138046,6 +138244,94 @@ module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1_ assign memory_r_addr = dmi__addr; endmodule +(* \nmigen.hierarchy = "test_issuer.ti.jtag.irblock" *) +(* generator = "nMigen" *) +module irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, posjtag_clk, ir); + reg \initial = 0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) + wire \$1 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) + wire \$11 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) + wire \$3 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) + wire \$5 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) + wire \$7 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) + wire \$9 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) + input TAP_bus__tdi; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + input capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) + output [3:0] ir; + reg [3:0] ir = 4'h1; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) + reg [3:0] \ir$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + input isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + input posjtag_clk; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) + input posjtag_rst; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + input shift; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *) + reg [3:0] shift_ir = 4'h0; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *) + reg [3:0] \shift_ir$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *) + output tdo; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + input update; + assign \$9 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift; + assign \$11 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update; + assign \$1 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture; + assign \$3 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift; + assign \$5 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update; + assign \$7 = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture; + always @(posedge posjtag_clk) + ir <= \ir$next ; + always @(posedge posjtag_clk) + shift_ir <= \shift_ir$next ; + always @* begin + if (\initial ) begin end + \shift_ir$next = shift_ir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *) + casez ({ \$5 , \$3 , \$1 }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" */ + 3'b??1: + \shift_ir$next = ir; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ + 3'b?1?: + \shift_ir$next = { TAP_bus__tdi, shift_ir[3:1] }; + endcase + end + always @* begin + if (\initial ) begin end + \ir$next = ir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *) + casez ({ \$11 , \$9 , \$7 }) + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" */ + 3'b??1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:143" */ + 3'b?1?: + /* empty */; + /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:145" */ + 3'b1??: + \ir$next = shift_ir; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (posjtag_rst) + 1'h1: + \ir$next = 4'h1; + endcase + end + assign tdo = ir[0]; +endmodule + (* \nmigen.hierarchy = "test_issuer.ti.jtag" *) (* generator = "nMigen" *) module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, rst, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__cyc, jtag_wb__we, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk); @@ -138444,34 +138730,38 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ wire \$450 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:801" *) wire \$453 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) + wire \$455 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) + wire \$457 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) - wire [30:0] \$455 ; + wire [30:0] \$459 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) - wire [30:0] \$456 ; + wire [30:0] \$460 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) - wire [30:0] \$458 ; + wire [30:0] \$462 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) - wire [30:0] \$459 ; + wire [30:0] \$463 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) - wire [7:0] \$461 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) - wire \$464 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) - wire \$466 ; + wire [7:0] \$465 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) wire \$468 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) wire \$47 ; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) wire \$470 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) + wire \$472 ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) + wire \$474 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) - wire [4:0] \$472 ; + wire [4:0] \$476 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) - wire [4:0] \$473 ; + wire [4:0] \$477 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) - wire [4:0] \$475 ; + wire [4:0] \$479 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) - wire [4:0] \$476 ; + wire [4:0] \$480 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" *) wire \$49 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) @@ -138541,27 +138831,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ input TAP_bus__tms; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" *) reg TAP_tdo; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) - wire _fsm_capture; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) - wire _fsm_isdr; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) - wire _fsm_isir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) - wire _fsm_shift; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) - wire _fsm_update; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *) - wire _idblock_TAP_id_tdo; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *) - wire _idblock_id_bypass; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) - wire _idblock_select_id; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) - wire [3:0] _irblock_ir; - (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *) - wire _irblock_tdo; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input clk; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) input dmi0__ack_o; @@ -138651,14 +138921,24 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ output eint_2__core__i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input eint_2__pad__i; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *) + wire fsm_capture; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *) + wire fsm_isdr; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *) + wire fsm_isir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *) + wire fsm_shift; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) reg [2:0] fsm_state = 3'h0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) - reg [2:0] \fsm_state$463 = 3'h0; + reg [2:0] \fsm_state$467 = 3'h0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) - reg [2:0] \fsm_state$463$next ; + reg [2:0] \fsm_state$467$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *) reg [2:0] \fsm_state$next ; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *) + wire fsm_update; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output gpio_e10__core__i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) @@ -138851,6 +139131,12 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ output gpio_s7__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output gpio_s7__pad__oe; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *) + wire idblock_TAP_id_tdo; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *) + wire idblock_id_bypass; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *) + wire idblock_select_id; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" *) reg [129:0] io_bd = 130'h000000000000000000000000000000000; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" *) @@ -138869,6 +139155,10 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ reg [129:0] \io_sr$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" *) wire io_update; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *) + wire [3:0] irblock_ir; + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *) + wire irblock_tdo; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) input jtag_wb__ack; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *) @@ -138989,7 +139279,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ wire posjtag_clk; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *) wire posjtag_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -139303,15 +139593,15 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ reg sr0_update_core_prev = 1'h0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) reg \sr0_update_core_prev$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) reg [2:0] sr5__i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) wire sr5__ie; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) wire [2:0] sr5__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) reg sr5__oe = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:99" *) reg \sr5__oe$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *) wire sr5_capture; @@ -139333,21 +139623,21 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ reg sr5_update_core_prev = 1'h0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *) reg \sr5_update_core_prev$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) output wb_dcache_en; reg wb_dcache_en = 1'h1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) - reg \wb_dcache_en$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + reg \wb_dcache_en$next ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) output wb_icache_en; reg wb_icache_en = 1'h1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) reg \wb_icache_en$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:97" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) reg wb_sram_en = 1'h1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:97" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) reg \wb_sram_en$next ; - assign \$9 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" *) 4'hf; + assign \$9 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" *) 4'hf; assign \$99 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[24] : sdr_dq_6__core__o; assign \$101 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[25] : sdr_dq_6__core__oe; assign \$103 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[26] : sdr_dq_7__pad__i; @@ -139358,7 +139648,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$113 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[31] : sdr_a_2__core__o; assign \$115 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[32] : sdr_a_3__core__o; assign \$117 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[33] : sdr_a_4__core__o; - assign \$11 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; + assign \$11 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; assign \$119 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[34] : sdr_a_5__core__o; assign \$121 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[35] : sdr_a_6__core__o; assign \$123 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[36] : sdr_a_7__core__o; @@ -139369,7 +139659,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$133 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[41] : sdr_clock__core__o; assign \$135 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[42] : sdr_cke__core__o; assign \$137 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[43] : sdr_ras_n__core__o; - assign \$13 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; + assign \$13 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; assign \$139 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[44] : sdr_cas_n__core__o; assign \$141 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[45] : sdr_we_n__core__o; assign \$143 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[46] : sdr_cs_n__core__o; @@ -139391,7 +139681,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$173 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[61] : sdr_dq_11__core__o; assign \$175 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[62] : sdr_dq_11__core__oe; assign \$177 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[63] : sdr_dq_12__pad__i; - assign \$17 = \$15 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *) _fsm_capture; + assign \$17 = \$15 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *) fsm_capture; assign \$179 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[64] : sdr_dq_12__core__o; assign \$181 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[65] : sdr_dq_12__core__oe; assign \$183 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[66] : sdr_dq_13__pad__i; @@ -139402,8 +139692,8 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$193 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[71] : sdr_dq_14__core__oe; assign \$195 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[72] : sdr_dq_15__pad__i; assign \$197 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[73] : sdr_dq_15__core__o; - assign \$1 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 1'h1; - assign \$19 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; + assign \$1 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 1'h1; + assign \$19 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; assign \$199 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[74] : sdr_dq_15__core__oe; assign \$201 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[75] : gpio_e8__pad__i; assign \$203 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[76] : gpio_e8__core__o; @@ -139414,7 +139704,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$213 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[81] : gpio_e10__pad__i; assign \$215 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[82] : gpio_e10__core__o; assign \$217 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[83] : gpio_e10__core__oe; - assign \$21 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; + assign \$21 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; assign \$219 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[84] : gpio_e11__pad__i; assign \$221 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[85] : gpio_e11__core__o; assign \$223 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[86] : gpio_e11__core__oe; @@ -139436,7 +139726,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$253 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[101] : gpio_s0__core__oe; assign \$255 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[102] : gpio_s1__pad__i; assign \$257 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[103] : gpio_s1__core__o; - assign \$25 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; + assign \$25 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; assign \$259 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[104] : gpio_s1__core__oe; assign \$261 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[105] : gpio_s2__pad__i; assign \$263 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[106] : gpio_s2__core__o; @@ -139458,85 +139748,85 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$293 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[121] : gpio_s7__core__o; assign \$295 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[122] : gpio_s7__core__oe; assign \$297 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[123] : mtwi_sda__pad__i; - assign \$29 = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$27 ; + assign \$29 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$27 ; assign \$299 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[124] : mtwi_sda__core__o; assign \$301 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[125] : mtwi_sda__core__oe; assign \$303 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[126] : mtwi_scl__core__o; assign \$305 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[127] : eint_0__pad__i; assign \$307 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[128] : eint_1__pad__i; assign \$309 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[129] : eint_2__pad__i; - assign \$311 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; - assign \$313 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; + assign \$311 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; + assign \$313 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; assign \$315 = \$311 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$313 ; - assign \$317 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; - assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) _fsm_shift; + assign \$317 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; + assign \$31 = \$29 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) fsm_shift; assign \$319 = \$315 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$317 ; - assign \$321 = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$319 ; - assign \$323 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h4; + assign \$321 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$319 ; + assign \$323 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h4; assign \$325 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$327 = \$325 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture; + assign \$327 = \$325 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; assign \$329 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$331 = \$329 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift; + assign \$331 = \$329 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; assign \$333 = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$335 = \$333 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update; + assign \$335 = \$333 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; assign \$337 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) sr0_update_core; - assign \$33 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; + assign \$33 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0; assign \$339 = sr0_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$337 ; - assign \$341 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h5; + assign \$341 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h5; assign \$343 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$345 = \$343 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture; + assign \$345 = \$343 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; assign \$347 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$349 = \$347 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift; + assign \$349 = \$347 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; assign \$351 = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$353 = \$351 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update; + assign \$353 = \$351 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; assign \$355 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) jtag_wb_addrsr_update_core; assign \$357 = jtag_wb_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$355 ; - assign \$35 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; - assign \$359 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h6; - assign \$361 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h7; + assign \$35 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2; + assign \$359 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h6; + assign \$361 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h7; assign \$363 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$365 = \$363 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture; + assign \$365 = \$363 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; assign \$367 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$369 = \$367 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift; + assign \$369 = \$367 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; assign \$371 = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$373 = \$371 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update; + assign \$373 = \$371 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; assign \$375 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) jtag_wb_datasr_update_core; assign \$377 = jtag_wb_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$375 ; assign \$37 = \$33 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$35 ; - assign \$379 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h8; + assign \$379 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h8; assign \$381 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$383 = \$381 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture; + assign \$383 = \$381 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; assign \$385 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$387 = \$385 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift; + assign \$387 = \$385 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; assign \$389 = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$391 = \$389 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update; + assign \$391 = \$389 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; assign \$393 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) dmi0_addrsr_update_core; assign \$395 = dmi0_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$393 ; - assign \$397 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h9; - assign \$3 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 4'hf; - assign \$39 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; - assign \$399 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'ha; + assign \$397 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h9; + assign \$3 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 4'hf; + assign \$39 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2; + assign \$399 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'ha; assign \$401 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$403 = \$401 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture; + assign \$403 = \$401 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; assign \$405 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$407 = \$405 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift; + assign \$407 = \$405 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; assign \$409 = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$411 = \$409 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update; + assign \$411 = \$409 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; assign \$413 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) dmi0_datasr_update_core; assign \$415 = dmi0_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$413 ; - assign \$417 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'hb; + assign \$417 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'hb; assign \$41 = \$37 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$39 ; assign \$419 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0; - assign \$421 = \$419 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture; + assign \$421 = \$419 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) fsm_capture; assign \$423 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0; - assign \$425 = \$423 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift; + assign \$425 = \$423 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) fsm_shift; assign \$427 = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0; - assign \$429 = \$427 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update; + assign \$429 = \$427 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) fsm_update; assign \$431 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) sr5_update_core; assign \$433 = sr5_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$431 ; assign \$435 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 1'h1; assign \$437 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 2'h2; - assign \$43 = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$41 ; + assign \$43 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$41 ; assign \$439 = \$435 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) \$437 ; assign \$441 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 2'h3; assign \$443 = \$439 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) \$441 ; @@ -139545,18 +139835,20 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$450 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) 1'h0; assign \$449 = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) \$450 ; assign \$453 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:801" *) 2'h2; - assign \$456 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) 1'h1; - assign \$45 = \$43 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) _fsm_update; - assign \$459 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) 1'h1; - assign \$461 = + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) dmi0__addr_i; - assign \$464 = \fsm_state$463 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 1'h1; - assign \$466 = \fsm_state$463 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 2'h2; - assign \$468 = \$464 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) \$466 ; - assign \$470 = \fsm_state$463 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) 2'h2; - assign \$473 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) 1'h1; - assign \$476 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) 1'h1; - assign \$47 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) 1'h0; - assign \$49 = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" *) 1'h0; + assign \$455 = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) 3'h4; + assign \$457 = \$453 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:802" *) \$455 ; + assign \$45 = \$43 & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) fsm_update; + assign \$460 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) 1'h1; + assign \$463 = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) 1'h1; + assign \$465 = + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) dmi0__addr_i; + assign \$468 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 1'h1; + assign \$470 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 2'h2; + assign \$472 = \$468 | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) \$470 ; + assign \$474 = \fsm_state$467 == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) 2'h2; + assign \$477 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) 1'h1; + assign \$47 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) 1'h0; + assign \$480 = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) 1'h1; + assign \$49 = irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" *) 1'h0; assign \$51 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[0] : mspi0_clk__core__o; assign \$53 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[1] : mspi0_cs_n__core__o; assign \$55 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[2] : mspi0_mosi__core__o; @@ -139572,7 +139864,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign \$73 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[11] : sdr_dq_2__pad__i; assign \$75 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[12] : sdr_dq_2__core__o; assign \$77 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[13] : sdr_dq_2__core__oe; - assign \$7 = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) \$5 ; + assign \$7 = fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) \$5 ; assign \$79 = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[14] : sdr_dq_3__pad__i; assign \$81 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[15] : sdr_dq_3__core__o; assign \$83 = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[16] : sdr_dq_3__core__oe; @@ -139594,7 +139886,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @(posedge clk) dmi0__din <= \dmi0__din$next ; always @(posedge clk) - \fsm_state$463 <= \fsm_state$463$next ; + \fsm_state$467 <= \fsm_state$467$next ; always @(posedge clk) dmi0__addr_i <= \dmi0__addr_i$next ; always @(posedge clk) @@ -139657,52 +139949,52 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ io_bd <= \io_bd$next ; always @(posedge posjtag_clk) io_sr <= \io_sr$next ; - _fsm _fsm ( + fsm fsm ( .TAP_bus__tck(TAP_bus__tck), .TAP_bus__tms(TAP_bus__tms), - .capture(_fsm_capture), - .isdr(_fsm_isdr), - .isir(_fsm_isir), + .capture(fsm_capture), + .isdr(fsm_isdr), + .isir(fsm_isir), .negjtag_clk(negjtag_clk), .negjtag_rst(negjtag_rst), .posjtag_clk(posjtag_clk), .posjtag_rst(posjtag_rst), - .shift(_fsm_shift), - .update(_fsm_update) + .shift(fsm_shift), + .update(fsm_update) ); - _idblock _idblock ( + idblock idblock ( .TAP_bus__tdi(TAP_bus__tdi), - .TAP_id_tdo(_idblock_TAP_id_tdo), - .capture(_fsm_capture), - .id_bypass(_idblock_id_bypass), + .TAP_id_tdo(idblock_TAP_id_tdo), + .capture(fsm_capture), + .id_bypass(idblock_id_bypass), .posjtag_clk(posjtag_clk), .posjtag_rst(posjtag_rst), - .select_id(_idblock_select_id), - .shift(_fsm_shift), - .update(_fsm_update) + .select_id(idblock_select_id), + .shift(fsm_shift), + .update(fsm_update) ); - _irblock _irblock ( + irblock irblock ( .TAP_bus__tdi(TAP_bus__tdi), - .capture(_fsm_capture), - .ir(_irblock_ir), - .isir(_fsm_isir), + .capture(fsm_capture), + .ir(irblock_ir), + .isir(fsm_isir), .posjtag_clk(posjtag_clk), .posjtag_rst(posjtag_rst), - .shift(_fsm_shift), - .tdo(_irblock_tdo), - .update(_fsm_update) + .shift(fsm_shift), + .tdo(irblock_tdo), + .update(fsm_update) ); always @* begin if (\initial ) begin end TAP_tdo = 1'h0; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" *) - casez ({ \$321 , _idblock_select_id, _fsm_isir }) + casez ({ \$321 , idblock_select_id, fsm_isir }) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" */ 3'b??1: - TAP_tdo = _irblock_tdo; + TAP_tdo = irblock_tdo; /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:417" */ 3'b?1?: - TAP_tdo = _idblock_TAP_id_tdo; + TAP_tdo = idblock_TAP_id_tdo; /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" */ 3'b1??: TAP_tdo = io_sr[129]; @@ -139711,7 +140003,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr0_update_core$next = sr0_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \sr0_update_core$next = 1'h0; @@ -139720,7 +140012,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr0_update_core_prev$next = sr0_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \sr0_update_core_prev$next = 1'h0; @@ -139728,6 +140020,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) casez (\$339 ) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ @@ -139737,7 +140030,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ default: \sr0__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \sr0__oe$next = 1'h0; @@ -139758,7 +140051,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: \sr0_reg$next = sr0__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (posjtag_rst) 1'h1: \sr0_reg$next = 3'h0; @@ -139767,7 +140060,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_addrsr_update_core$next = jtag_wb_addrsr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb_addrsr_update_core$next = 1'h0; @@ -139776,7 +140069,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_addrsr_update_core_prev$next = jtag_wb_addrsr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb_addrsr_update_core_prev$next = 1'h0; @@ -139784,6 +140077,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) casez (\$357 ) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ @@ -139793,7 +140087,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ default: \jtag_wb_addrsr__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb_addrsr__oe$next = 1'h0; @@ -139814,7 +140108,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: \jtag_wb_addrsr_reg$next = jtag_wb_addrsr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (posjtag_rst) 1'h1: \jtag_wb_addrsr_reg$next = 30'h00000000; @@ -139823,7 +140117,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_datasr_update_core$next = jtag_wb_datasr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb_datasr_update_core$next = 1'h0; @@ -139832,7 +140126,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \jtag_wb_datasr_update_core_prev$next = jtag_wb_datasr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb_datasr_update_core_prev$next = 1'h0; @@ -139840,6 +140134,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) casez (\$377 ) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ @@ -139849,7 +140144,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ default: \jtag_wb_datasr__oe$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb_datasr__oe$next = 2'h0; @@ -139870,7 +140165,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: \jtag_wb_datasr_reg$next = jtag_wb_datasr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (posjtag_rst) 1'h1: \jtag_wb_datasr_reg$next = 32'd0; @@ -139879,7 +140174,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_addrsr_update_core$next = dmi0_addrsr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0_addrsr_update_core$next = 1'h0; @@ -139888,7 +140183,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_addrsr_update_core_prev$next = dmi0_addrsr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0_addrsr_update_core_prev$next = 1'h0; @@ -139896,6 +140191,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) casez (\$395 ) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ @@ -139905,7 +140201,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ default: \dmi0_addrsr__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0_addrsr__oe$next = 1'h0; @@ -139926,7 +140222,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: \dmi0_addrsr_reg$next = dmi0_addrsr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (posjtag_rst) 1'h1: \dmi0_addrsr_reg$next = 8'h00; @@ -139935,7 +140231,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_datasr_update_core$next = dmi0_datasr_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0_datasr_update_core$next = 1'h0; @@ -139944,7 +140240,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \dmi0_datasr_update_core_prev$next = dmi0_datasr_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0_datasr_update_core_prev$next = 1'h0; @@ -139952,6 +140248,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) casez (\$415 ) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ @@ -139961,7 +140258,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ default: \dmi0_datasr__oe$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0_datasr__oe$next = 2'h0; @@ -139982,7 +140279,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: \dmi0_datasr_reg$next = dmi0_datasr__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (posjtag_rst) 1'h1: \dmi0_datasr_reg$next = 64'h0000000000000000; @@ -139991,7 +140288,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr5_update_core$next = sr5_update; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \sr5_update_core$next = 1'h0; @@ -140000,7 +140297,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ always @* begin if (\initial ) begin end \sr5_update_core_prev$next = sr5_update_core; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \sr5_update_core_prev$next = 1'h0; @@ -140008,6 +140305,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) casez (\$433 ) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" */ @@ -140017,7 +140315,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ default: \sr5__oe$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \sr5__oe$next = 1'h0; @@ -140038,7 +140336,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: \sr5_reg$next = sr5__i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (posjtag_rst) 1'h1: \sr5_reg$next = 3'h0; @@ -140046,6 +140344,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" *) casez ({ sr5_shift, dmi0_datasr_shift, dmi0_addrsr_shift, jtag_wb_datasr_shift, jtag_wb_addrsr_shift, sr0_shift }) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" */ @@ -140086,7 +140385,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ \jtag_wb__adr$next = jtag_wb_addrsr__o; /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:759" */ 3'b?1?: - \jtag_wb__adr$next = \$455 [29:0]; + \jtag_wb__adr$next = \$459 [29:0]; endcase /* \nmigen.decoding = "READ/1" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:766" */ @@ -140107,10 +140406,10 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ casez (jtag_wb__ack) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" */ 1'h1: - \jtag_wb__adr$next = \$458 [29:0]; + \jtag_wb__adr$next = \$462 [29:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb__adr$next = 30'h00000000; @@ -140163,7 +140462,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ \fsm_state$next = 3'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \fsm_state$next = 3'h0; @@ -140190,7 +140489,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ \jtag_wb__dat_w$next = jtag_wb_datasr__o; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb__dat_w$next = 32'd0; @@ -140219,7 +140518,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ \jtag_wb_datasr__i$next = jtag_wb__dat_r; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_wb_datasr__i$next = 32'd0; @@ -140229,7 +140528,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ if (\initial ) begin end \dmi0__addr_i$next = dmi0__addr_i; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) - casez (\fsm_state$463 ) + casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ 3'h0: @@ -140240,7 +140539,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ \dmi0__addr_i$next = dmi0_addrsr__o[3:0]; /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:492" */ 3'b?1?: - \dmi0__addr_i$next = \$472 [3:0]; + \dmi0__addr_i$next = \$476 [3:0]; endcase /* \nmigen.decoding = "READ/1" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:501" */ @@ -140261,10 +140560,10 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ casez (dmi0__ack_o) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" */ 1'h1: - \dmi0__addr_i$next = \$475 [3:0]; + \dmi0__addr_i$next = \$479 [3:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0__addr_i$next = 4'h0; @@ -140272,9 +140571,9 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ end always @* begin if (\initial ) begin end - \fsm_state$463$next = \fsm_state$463 ; + \fsm_state$467$next = \fsm_state$467 ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) - casez (\fsm_state$463 ) + casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ 3'h0: @@ -140282,18 +140581,18 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ casez ({ dmi0_datasr__oe, dmi0_addrsr__oe }) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" */ 3'b??1: - \fsm_state$463$next = 3'h1; + \fsm_state$467$next = 3'h1; /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:492" */ 3'b?1?: - \fsm_state$463$next = 3'h1; + \fsm_state$467$next = 3'h1; /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:496" */ 3'b1??: - \fsm_state$463$next = 3'h2; + \fsm_state$467$next = 3'h2; endcase /* \nmigen.decoding = "READ/1" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:501" */ 3'h1: - \fsm_state$463$next = 3'h3; + \fsm_state$467$next = 3'h3; /* \nmigen.decoding = "READACK/3" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:505" */ 3'h3: @@ -140301,12 +140600,12 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ casez (dmi0__ack_o) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" */ 1'h1: - \fsm_state$463$next = 3'h0; + \fsm_state$467$next = 3'h0; endcase /* \nmigen.decoding = "WRRD/2" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:512" */ 3'h2: - \fsm_state$463$next = 3'h4; + \fsm_state$467$next = 3'h4; /* \nmigen.decoding = "WRRDACK/4" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:516" */ 3'h4: @@ -140314,20 +140613,20 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ casez (dmi0__ack_o) /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" */ 1'h1: - \fsm_state$463$next = 3'h1; + \fsm_state$467$next = 3'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: - \fsm_state$463$next = 3'h0; + \fsm_state$467$next = 3'h0; endcase end always @* begin if (\initial ) begin end \dmi0__din$next = dmi0__din; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) - casez (\fsm_state$463 ) + casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ 3'h0: @@ -140344,7 +140643,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ \dmi0__din$next = dmi0_datasr__o; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0__din$next = 64'h0000000000000000; @@ -140354,7 +140653,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ if (\initial ) begin end \dmi0_datasr__i$next = dmi0_datasr__i; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *) - casez (\fsm_state$463 ) + casez (\fsm_state$467 ) /* \nmigen.decoding = "IDLE/0" */ /* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:488" */ 3'h0: @@ -140373,7 +140672,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ \dmi0_datasr__i$next = dmi0__dout; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dmi0_datasr__i$next = 64'h0000000000000000; @@ -140390,7 +140689,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 1'h1: { \wb_sram_en$next , \wb_dcache_en$next , \wb_icache_en$next } = sr5__o; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: begin @@ -140422,7 +140721,7 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 3'b?1?: \io_sr$next = { io_sr[128:0], TAP_bus__tdi }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (posjtag_rst) 1'h1: \io_sr$next = 130'h000000000000000000000000000000000; @@ -140443,22 +140742,22 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ 3'b1??: \io_bd$next = io_sr; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (negjtag_rst) 1'h1: \io_bd$next = 130'h000000000000000000000000000000000; endcase end - assign \$455 = \$456 ; - assign \$458 = \$459 ; - assign \$472 = \$473 ; - assign \$475 = \$476 ; + assign \$459 = \$460 ; + assign \$462 = \$463 ; + assign \$476 = \$477 ; + assign \$479 = \$480 ; assign sr5__ie = 1'h0; assign sr0__i = sr0__o; - assign dmi0__we_i = \$470 ; - assign dmi0__req_i = \$468 ; - assign dmi0_addrsr__i = \$461 ; - assign jtag_wb__we = \$453 ; + assign dmi0__we_i = \$474 ; + assign dmi0__req_i = \$472 ; + assign dmi0_addrsr__i = \$465 ; + assign jtag_wb__we = \$457 ; assign jtag_wb__cyc = \$449 ; assign jtag_wb__stb = \$447 ; assign jtag_wb__sel[3] = 1'h1; @@ -140631,16 +140930,16 @@ module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0_ assign io_update = \$45 ; assign io_shift = \$31 ; assign io_capture = \$17 ; - assign _idblock_id_bypass = \$9 ; - assign _idblock_select_id = \$7 ; + assign idblock_id_bypass = \$9 ; + assign idblock_select_id = \$7 ; endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.l0" *) (* generator = "nMigen" *) module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -140740,7 +141039,7 @@ module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_ wire pimem_x_st_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *) wire pimem_x_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) input wb_dcache_en; \l0$130 l0 ( .coresync_clk(coresync_clk), @@ -140846,9 +141145,9 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ wire [95:0] \$31 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *) wire [95:0] \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg \idx_l$23 = 1'h0; @@ -141102,7 +141401,7 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ 1'h1: \idx_l$23$next = pick_o; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \idx_l$23$next = 1'h0; @@ -141260,9 +141559,9 @@ module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -141291,7 +141590,7 @@ module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_c always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -141520,9 +141819,9 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, wire \alu_ok$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" *) wire alu_valid; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input cu_ad__go_i; @@ -142289,7 +142588,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -142298,7 +142597,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \opc_l_r_opc$next = reset_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -142307,7 +142606,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -142316,7 +142615,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -142325,7 +142624,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \adr_l_r_adr$next = reset_a; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \adr_l_r_adr$next = 1'h1; @@ -142334,7 +142633,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \wri_l_r_wri$next = \$38 [0]; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \wri_l_r_wri$next = 1'h1; @@ -142343,7 +142642,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \upd_l_s_upd$next = reset_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \upd_l_s_upd$next = 1'h0; @@ -142352,7 +142651,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \upd_l_r_upd$next = reset_u; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \upd_l_r_upd$next = 1'h1; @@ -142361,7 +142660,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \sto_l_r_sto$next = \$59 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \sto_l_r_sto$next = 1'h1; @@ -142370,7 +142669,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \lsd_l_r_lsd$next = \$63 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \lsd_l_r_lsd$next = 1'h1; @@ -142406,7 +142705,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, 1'h1: { \oper_r__insn$next , \oper_r__ldst_mode$next , \oper_r__sign_extend$next , \oper_r__byte_reverse$next , \oper_r__data_len$next , \oper_r__is_signed$next , \oper_r__is_32bit$next , \oper_r__oe__ok$next , \oper_r__oe__oe$next , \oper_r__rc__ok$next , \oper_r__rc__rc$next , \oper_r__zero_a$next , \oper_r__imm_data__ok$next , \oper_r__imm_data__data$next , \oper_r__fn_unit$next , \oper_r__insn_type$next } = 133'h0000000000000000000000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -142510,7 +142809,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, always @* begin if (\initial ) begin end \ldst_port0_addr_i_ok$next = \$177 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ldst_port0_addr_i_ok$next = 1'h0; @@ -142542,6 +142841,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *) casez (oper_r__byte_reverse) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" */ @@ -142554,10 +142854,12 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" *) casez (oper_r__sign_extend) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) casez (\$192 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" */ @@ -142598,6 +142900,7 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *) casez (oper_r__byte_reverse) /* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" */ @@ -143313,9 +143616,9 @@ module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -143344,7 +143647,7 @@ module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -143695,9 +143998,9 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output cr_a_ok; @@ -144198,7 +144501,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -144207,7 +144510,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$63 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -144216,7 +144519,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -144225,7 +144528,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -144234,7 +144537,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -144243,7 +144546,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -144252,7 +144555,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -144261,7 +144564,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -144270,7 +144573,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \req_l_s_req$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 2'h0; @@ -144279,7 +144582,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \req_l_r_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 2'h3; @@ -144311,7 +144614,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \alu_logical0_logical_op__insn$next , \alu_logical0_logical_op__data_len$next , \alu_logical0_logical_op__is_signed$next , \alu_logical0_logical_op__is_32bit$next , \alu_logical0_logical_op__output_carry$next , \alu_logical0_logical_op__write_cr0$next , \alu_logical0_logical_op__invert_out$next , \alu_logical0_logical_op__input_carry$next , \alu_logical0_logical_op__zero_a$next , \alu_logical0_logical_op__invert_in$next , \alu_logical0_logical_op__oe__ok$next , \alu_logical0_logical_op__oe__oe$next , \alu_logical0_logical_op__rc__ok$next , \alu_logical0_logical_op__rc__rc$next , \alu_logical0_logical_op__imm_data__ok$next , \alu_logical0_logical_op__imm_data__data$next , \alu_logical0_logical_op__fn_unit$next , \alu_logical0_logical_op__insn_type$next } = { oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -144340,7 +144643,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -144362,7 +144665,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -144401,7 +144704,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -144410,7 +144713,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -144439,7 +144742,7 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical always @* begin if (\initial ) begin end \prev_wr_go$next = \$19 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 2'h0; @@ -144485,9 +144788,9 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -145731,7 +146034,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -145779,7 +146082,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -145805,7 +146108,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -145824,7 +146127,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -145843,7 +146146,7 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn 2'b1?: { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -145880,9 +146183,9 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$49 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) input [3:0] cr_a; @@ -146796,7 +147099,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -146844,7 +147147,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -146870,7 +147173,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: { \o_ok$21$next , \o$20$next } = { \o_ok$71 , \o$70 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$21$next = 1'h0; @@ -146889,7 +147192,7 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn 2'b1?: { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$73 , \cr_a$72 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$23$next = 1'h0; @@ -146931,9 +147234,9 @@ module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -146962,7 +147265,7 @@ module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -147073,9 +147376,9 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ wire \$93 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) wire \$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -147136,7 +147439,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ reg \m_store_err_o$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *) input m_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) input wb_dcache_en; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *) input [47:0] x_addr_i; @@ -147245,7 +147548,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__cyc$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dbus__cyc$next = 1'h0; @@ -147273,7 +147576,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__stb$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dbus__stb$next = 1'h0; @@ -147296,6 +147599,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ casez (wb_dcache_en) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) casez (\$95 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" */ @@ -147314,6 +147618,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ casez (wb_dcache_en) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) casez ({ \$35 , dbus__cyc }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ @@ -147332,7 +147637,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__sel$next = 8'h00; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dbus__sel$next = 8'h00; @@ -147357,7 +147662,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \m_ld_data_o$next = 64'h0000000000000000; @@ -147370,6 +147675,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ casez (wb_dcache_en) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) casez ({ \$63 , dbus__cyc }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ @@ -147383,7 +147689,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__adr$next = 45'h000000000000; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dbus__adr$next = 45'h000000000000; @@ -147396,6 +147702,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ casez (wb_dcache_en) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) casez ({ \$71 , dbus__cyc }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ @@ -147409,7 +147716,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__we$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dbus__we$next = 1'h0; @@ -147422,6 +147729,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ casez (wb_dcache_en) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *) casez ({ \$79 , dbus__cyc }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" */ @@ -147435,7 +147743,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \dbus__dat_w$next = 64'h0000000000000000; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \dbus__dat_w$next = 64'h0000000000000000; @@ -147458,7 +147766,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_load_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \m_load_err_o$next = 1'h0; @@ -147481,7 +147789,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_store_err_o$next = 1'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \m_store_err_o$next = 1'h0; @@ -147501,7 +147809,7 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ \m_badaddr_o$next = dbus__adr; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \m_badaddr_o$next = 45'h000000000000; @@ -148048,6 +148356,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) casez ({ is_32bit, \$26 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */ @@ -148055,6 +148364,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ a_i = ra; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" */ 2'b1?: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" *) casez (alu_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" */ @@ -148088,6 +148398,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) casez (\$71 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ @@ -148095,6 +148406,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ tval[2] = 1'h1; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ default: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) casez (\$73 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */ @@ -148115,6 +148427,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) casez (\$81 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ @@ -148134,6 +148447,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) casez (\$87 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ @@ -148153,6 +148467,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* \nmigen.decoding = "OP_CMP/10" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" */ 7'h0a: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) casez (\$93 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" */ @@ -148160,6 +148475,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" */ default: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) casez (\$95 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" */ @@ -148182,6 +148498,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ 7'h0a: begin cr_a[1:0] = { tval[2], xer_so }; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" *) casez (alu_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" */ @@ -148314,6 +148631,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) casez ({ is_32bit, \$28 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" */ @@ -148321,6 +148639,7 @@ module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__ b_i = rb; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" */ 2'b1?: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" *) casez (alu_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" */ @@ -148884,6 +149203,7 @@ module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op always @* begin if (\initial ) begin end o_ok = 1'h1; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" *) casez (sr_op__insn_type) /* \nmigen.decoding = "OP_SHL/60" */ @@ -148998,7 +149318,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o wire [64:0] \$35 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) wire [64:0] \$36 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) wire [63:0] \$38 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) wire \$40 ; @@ -149284,7 +149604,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o assign \$31 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) \$29 ; assign \$33 = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) cr_bit; assign \$36 = fast1 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) 1'h1; - assign \$38 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) fast1[31:0]; + assign \$38 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) fast1[31:0]; assign \$40 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) ctr_n; assign \$42 = bo[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) \$40 ; assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) br_op__insn[6]; @@ -149292,6 +149612,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o assign \$49 = br_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) 3'h4; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) casez (\$14 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" */ @@ -149318,6 +149639,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o /* \nmigen.decoding = "OP_BCREG/8" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" */ 7'h08: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) casez (\$46 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" */ @@ -149389,7 +149711,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o end always @* begin if (\initial ) begin end - cr_bit = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" *) casez (bi) 2'h0: @@ -149405,6 +149727,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o always @* begin if (\initial ) begin end ctr_write = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) casez (bo[2]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ @@ -149418,6 +149741,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o always @* begin if (\initial ) begin end bc_taken = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) casez (bo[2]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ @@ -149442,6 +149766,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o always @* begin if (\initial ) begin end ctr_n = 64'h0000000000000000; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) casez (bo[2]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ @@ -149455,6 +149780,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o always @* begin if (\initial ) begin end \fast1$10 = 64'h0000000000000000; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) casez (bo[2]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ @@ -149468,6 +149794,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o always @* begin if (\initial ) begin end ctr_m = 64'h0000000000000000; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) casez (bo[2]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ @@ -149475,6 +149802,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o /* empty */; /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" */ default: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" *) casez (br_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" */ @@ -149489,6 +149817,7 @@ module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_o always @* begin if (\initial ) begin end ctr_zero_bo1 = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *) casez (bo[2]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" */ @@ -149514,9 +149843,9 @@ endmodule (* generator = "nMigen" *) module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , o, o_ok, \fast1$11 , fast1_ok, \fast2$12 , fast2_ok, nia, nia_ok, msr, msr_ok, muxid); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) wire [63:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) wire [63:0] \$15 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *) wire \$17 ; @@ -149888,8 +150217,8 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m reg \trapexc_$signal$69 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *) reg \trapexc_$signal$70 ; - assign \$13 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) ra[31:0]; - assign \$15 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) rb[31:0]; + assign \$13 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ra[31:0]; + assign \$15 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) rb[31:0]; assign \$17 = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *) $signed(b_s); assign \$19 = $signed(a_s) > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" *) $signed(b_s); assign \$21 = a < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *) b; @@ -149927,6 +150256,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m assign \$93 = \$89 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) \$91 ; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) casez (trap_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ @@ -150210,6 +150540,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) casez (trap_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ @@ -150260,6 +150591,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m 7'h48, 7'h4a: begin { msr_ok, msr } = \$75 ; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" *) casez (trap_op__insn[21]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" */ @@ -150271,6 +150603,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" */ default: begin + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) casez (\$77 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" */ @@ -150333,6 +150666,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m casez (\$87 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" *) casez (trap_op__msr[60]) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" */ @@ -150429,6 +150763,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) casez (trap_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ @@ -150441,6 +150776,7 @@ module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__m end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *) casez (trap_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" */ @@ -151032,6 +151368,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat if (\initial ) begin end o = 64'h0000000000000000; o_ok = 1'h1; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *) casez (logical_op__insn_type) /* \nmigen.decoding = "OP_AND/4" */ @@ -151057,6 +151394,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat /* \nmigen.decoding = "OP_PRTY/55" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" */ 7'h37: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) casez (\$155 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" */ @@ -151441,6 +151779,7 @@ module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_dat /* \nmigen.decoding = "OP_CNTZ/14" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" */ 7'h0e: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" *) casez (logical_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" */ @@ -151759,6 +152098,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, 7'h45: begin \cr_a$6 = cr_c; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" *) casez (bt) 2'h0: @@ -151831,6 +152171,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" */ 7'h3b: begin + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" *) casez ({ cr_a[2], cr_a[3] }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" */ @@ -151900,6 +152241,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_ISEL/35" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" */ 7'h23: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" *) casez (BC) 2'h0: @@ -151985,6 +152327,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_CROP/69" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ 7'h45: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" *) casez (ba) 2'h0: @@ -152010,6 +152353,7 @@ module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, /* \nmigen.decoding = "OP_CROP/69" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" */ 7'h45: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" *) casez (bb) 2'h0: @@ -152386,9 +152730,9 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output cr_a_ok; @@ -152892,7 +153236,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -152901,7 +153245,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -152910,7 +153254,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -152919,7 +153263,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -152928,7 +153272,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -152937,7 +153281,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -152946,7 +153290,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 3'h0; @@ -152955,7 +153299,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 3'h7; @@ -152964,7 +153308,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 4'h0; @@ -152973,7 +153317,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 4'hf; @@ -152999,7 +153343,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \alu_mul0_mul_op__insn$next , \alu_mul0_mul_op__is_signed$next , \alu_mul0_mul_op__is_32bit$next , \alu_mul0_mul_op__write_cr0$next , \alu_mul0_mul_op__oe__ok$next , \alu_mul0_mul_op__oe__oe$next , \alu_mul0_mul_op__rc__ok$next , \alu_mul0_mul_op__rc__rc$next , \alu_mul0_mul_op__imm_data__ok$next , \alu_mul0_mul_op__imm_data__data$next , \alu_mul0_mul_op__fn_unit$next , \alu_mul0_mul_op__insn_type$next } = { oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -153028,7 +153372,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -153050,7 +153394,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -153072,7 +153416,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r2__xer_ov_ok$next , \data_r2__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__xer_ov_ok$next = 1'h0; @@ -153094,7 +153438,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -153133,7 +153477,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$88 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -153142,7 +153486,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$90 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -153191,7 +153535,7 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 4'h0; @@ -154189,6 +154533,7 @@ module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__ /* \nmigen.decoding = "OP_MUL_L64/50" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" */ 7'h32: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" *) casez (is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" */ @@ -154252,9 +154597,9 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -155323,7 +155668,7 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -155365,7 +155710,7 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m 2'b1?: { \mul_op__insn$next , \mul_op__is_signed$next , \mul_op__is_32bit$next , \mul_op__write_cr0$next , \mul_op__oe__ok$next , \mul_op__oe__oe$next , \mul_op__rc__ok$next , \mul_op__rc__rc$next , \mul_op__imm_data__ok$next , \mul_op__imm_data__data$next , \mul_op__fn_unit$next , \mul_op__insn_type$next } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -155473,9 +155818,9 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$34 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* enum_base_type = "Function" *) (* enum_value_00000000000000 = "NONE" *) @@ -156264,7 +156609,7 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -156306,7 +156651,7 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -156397,9 +156742,9 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -157533,7 +157878,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -157575,7 +157920,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \mul_op__insn$13$next , \mul_op__is_signed$12$next , \mul_op__is_32bit$11$next , \mul_op__write_cr0$10$next , \mul_op__oe__ok$9$next , \mul_op__oe__oe$8$next , \mul_op__rc__ok$7$next , \mul_op__rc__rc$6$next , \mul_op__imm_data__ok$5$next , \mul_op__imm_data__data$4$next , \mul_op__fn_unit$3$next , \mul_op__insn_type$2$next } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -157601,7 +157946,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \o_ok$next , \o$14$next } = { \o_ok$72 , \o$71 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -157620,7 +157965,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$74 , \cr_a$73 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -157639,7 +157984,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$76 , \xer_ov$75 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -157658,7 +158003,7 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m 2'b1?: { \xer_so_ok$next , \xer_so$15$next } = { \xer_so_ok$78 , \xer_so$77 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -158101,9 +158446,9 @@ module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158132,7 +158477,7 @@ module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158163,9 +158508,9 @@ module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158194,7 +158539,7 @@ module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158225,9 +158570,9 @@ module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158256,7 +158601,7 @@ module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158287,9 +158632,9 @@ module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158318,7 +158663,7 @@ module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158349,9 +158694,9 @@ module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158380,7 +158725,7 @@ module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158411,9 +158756,9 @@ module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158442,7 +158787,7 @@ module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158473,9 +158818,9 @@ module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158504,7 +158849,7 @@ module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158535,9 +158880,9 @@ module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158566,7 +158911,7 @@ module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158597,9 +158942,9 @@ module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158628,7 +158973,7 @@ module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -158659,9 +159004,9 @@ module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -158690,7 +159035,7 @@ module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -159070,6 +159415,7 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ assign \$52 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *) casez (oe) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ @@ -159082,6 +159428,7 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) casez (\$45 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ @@ -159094,6 +159441,7 @@ module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) casez (alu_op__invert_out) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ @@ -159488,6 +159836,7 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, assign \$41 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *) casez (oe) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ @@ -159500,6 +159849,7 @@ module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) casez (\$34 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ @@ -159898,6 +160248,7 @@ module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_ assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) casez (\$36 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ @@ -160260,6 +160611,7 @@ module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) casez (logical_op__invert_out) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ @@ -160272,6 +160624,7 @@ module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) casez (\$40 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ @@ -160660,6 +161013,7 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d assign \$51 = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0]; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *) casez (oe) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" */ @@ -160672,6 +161026,7 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) casez (\$44 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" */ @@ -160684,6 +161039,7 @@ module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *) casez (logical_op__invert_out) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" */ @@ -160767,7 +161123,7 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ wire [64:0] \$29 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) wire [64:0] \$30 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) wire [64:0] \$32 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) wire [64:0] \$34 ; @@ -161103,7 +161459,7 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ assign \$25 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) quotient_root; assign \$27 = quotient_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) \$23 : \$25 ; assign \$30 = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) remainder[127:64]; - assign \$32 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) remainder[127:64]; + assign \$32 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) remainder[127:64]; assign \$34 = remainder_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) \$30 : \$32 ; assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) logical_op__is_32bit; assign \$38 = quotient_65[64] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) quotient_65[63]; @@ -161128,10 +161484,12 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ /* \nmigen.decoding = "OP_DIVE/30" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" */ 7'h1e: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" *) casez (logical_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" *) casez (logical_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" */ @@ -161148,10 +161506,12 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ /* \nmigen.decoding = "OP_DIV/29" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" */ 7'h1d: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" *) casez (logical_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" *) casez (logical_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" */ @@ -161168,10 +161528,12 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ /* \nmigen.decoding = "OP_MOD/47" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" */ 7'h2f: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" *) casez (logical_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" *) casez (logical_op__is_signed) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" */ @@ -161190,6 +161552,7 @@ module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" *) casez ({ logical_op__is_signed, \$36 , div_by_zero }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" */ @@ -161670,9 +162033,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu wire \$17 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$19 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) wire [3:0] \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) wire [3:0] \$23 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) wire \$25 ; @@ -161766,9 +162129,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu reg busy_l_r_busy; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg busy_l_s_busy; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire cyc_l_q_cyc; @@ -161909,8 +162272,8 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu assign \$17 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) sts_dly; assign \$1 = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok; assign \$19 = sts & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ; - assign \$21 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) ldst_port0_addr_i[2:0]; - assign \$23 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) ldst_port0_addr_i[2:0]; + assign \$21 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ldst_port0_addr_i[2:0]; + assign \$23 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:269" *) ldst_port0_addr_i[2:0]; assign \$25 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; assign \$27 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; assign \$29 = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked; @@ -162031,7 +162394,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu 1'h1: \st_done_s_st_done$next = 1'h1; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \st_done_s_st_done$next = 1'h0; @@ -162050,7 +162413,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \busy_delay$next = ldst_port0_busy_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \busy_delay$next = 1'h0; @@ -162336,7 +162699,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu \fsm_state$next = 2'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \fsm_state$next = 2'h0; @@ -162355,7 +162718,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu always @* begin if (\initial ) begin end \lsui_active_dly$next = lsui_active; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \lsui_active_dly$next = 1'h0; @@ -162427,7 +162790,7 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \adrok_l_s_addr_acked$next = 1'h0; @@ -162478,9 +162841,9 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_a; @@ -163145,7 +163508,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -163192,7 +163555,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: { \o_ok$next , \o$next } = { \o_ok$21 , \o$20 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -163211,7 +163574,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: { \full_cr_ok$next , \full_cr$5$next } = { \full_cr_ok$23 , \full_cr$22 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \full_cr_ok$next = 1'h0; @@ -163230,7 +163593,7 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ 2'b1?: { \cr_a_ok$next , \cr_a$6$next } = { \cr_a_ok$25 , \cr_a$24 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -163604,9 +163967,9 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i reg \br_op__lk$8 = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \br_op__lk$8$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [3:0] cr_a; @@ -163999,7 +164362,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -164037,7 +164400,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \br_op__is_32bit$9$next , \br_op__lk$8$next , \br_op__imm_data__ok$7$next , \br_op__imm_data__data$6$next , \br_op__insn$5$next , \br_op__fn_unit$4$next , \br_op__insn_type$3$next , \br_op__cia$2$next } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -164059,7 +164422,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \fast1_ok$next , \fast1$10$next } = { \fast1_ok$36 , \fast1$35 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -164078,7 +164441,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \fast2_ok$next , \fast2$11$next } = { \fast2_ok$38 , \fast2$37 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \fast2_ok$next = 1'h0; @@ -164097,7 +164460,7 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i 2'b1?: { \nia_ok$next , \nia$next } = { \nia_ok$40 , \nia$39 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \nia_ok$next = 1'h0; @@ -164126,9 +164489,9 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; @@ -164882,7 +165245,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -164930,7 +165293,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \o_ok$next , \o$next } = { \o_ok$30 , \o$29 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -164949,7 +165312,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \spr1_ok$next , \spr1$6$next } = { \spr1_ok$32 , \spr1$31 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \spr1_ok$next = 1'h0; @@ -164968,7 +165331,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \fast1_ok$next , \fast1$7$next } = { \fast1_ok$34 , \fast1$33 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -164987,7 +165350,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \xer_so_ok$next , \xer_so$8$next } = { \xer_so_ok$36 , \xer_so$35 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -165006,7 +165369,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \xer_ov_ok$next , \xer_ov$9$next } = { \xer_ov_ok$38 , \xer_ov$37 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -165025,7 +165388,7 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s 2'b1?: { \xer_ca_ok$next , \xer_ca$10$next } = { \xer_ca_ok$40 , \xer_ca$39 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -165504,9 +165867,9 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o wire \alu_op__zero_a$79 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) reg \alu_op__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -166368,7 +166731,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$91 , \cr_a$90 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -166387,7 +166750,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$93 , \xer_ca$92 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -166406,7 +166769,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$95 , \xer_ov$94 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -166425,7 +166788,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$97 , \xer_so$96 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -166443,7 +166806,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -166491,7 +166854,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \alu_op__insn$next , \alu_op__data_len$next , \alu_op__is_signed$next , \alu_op__is_32bit$next , \alu_op__output_carry$next , \alu_op__input_carry$next , \alu_op__write_cr0$next , \alu_op__invert_out$next , \alu_op__zero_a$next , \alu_op__invert_in$next , \alu_op__oe__ok$next , \alu_op__oe__oe$next , \alu_op__rc__ok$next , \alu_op__rc__rc$next , \alu_op__imm_data__ok$next , \alu_op__imm_data__data$next , \alu_op__fn_unit$next , \alu_op__insn_type$next } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -166517,7 +166880,7 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o 2'b1?: { \o_ok$next , \o$next } = { \o_ok$89 , \o$88 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -166556,9 +166919,9 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$65 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -167824,7 +168187,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \xer_ca_ok$next , \xer_ca$next } = { \xer_ca_ok$95 , \xer_ca$94 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ca_ok$next = 1'h0; @@ -167842,7 +168205,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -167889,7 +168252,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \sr_op__insn$next , \sr_op__is_signed$next , \sr_op__is_32bit$next , \sr_op__output_cr$next , \sr_op__input_cr$next , \sr_op__output_carry$next , \sr_op__input_carry$next , \sr_op__invert_in$next , \sr_op__write_cr0$next , \sr_op__oe__ok$next , \sr_op__oe__oe$next , \sr_op__rc__ok$next , \sr_op__rc__rc$next , \sr_op__imm_data__ok$next , \sr_op__imm_data__data$next , \sr_op__fn_unit$next , \sr_op__insn_type$next } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -167915,7 +168278,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \o_ok$next , \o$next } = { \o_ok$86 , \o$85 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -167934,7 +168297,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$88 , \cr_a$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -167953,7 +168316,7 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, 2'b1?: { \xer_so_ok$next , \xer_so$next } = { \xer_so_ok$92 , \xer_so$91 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -167996,9 +168359,9 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) wire [63:0] dummy_fast1; @@ -168731,7 +169094,7 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -169292,9 +169655,9 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o reg \alu_op__zero_a$11$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) wire \alu_op__zero_a$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) input [3:0] cr_a; @@ -169854,7 +170217,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -169902,7 +170265,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \alu_op__insn$19$next , \alu_op__data_len$18$next , \alu_op__is_signed$17$next , \alu_op__is_32bit$16$next , \alu_op__output_carry$15$next , \alu_op__input_carry$14$next , \alu_op__write_cr0$13$next , \alu_op__invert_out$12$next , \alu_op__zero_a$11$next , \alu_op__invert_in$10$next , \alu_op__oe__ok$9$next , \alu_op__oe__oe$8$next , \alu_op__rc__ok$7$next , \alu_op__rc__rc$6$next , \alu_op__imm_data__ok$5$next , \alu_op__imm_data__data$4$next , \alu_op__fn_unit$3$next , \alu_op__insn_type$2$next } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -169928,7 +170291,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \o_ok$21$next , \o$20$next } = { \o_ok$82 , \o$81 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$21$next = 1'h0; @@ -169947,7 +170310,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \cr_a_ok$23$next , \cr_a$22$next } = { \cr_a_ok$84 , \cr_a$83 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$23$next = 1'h0; @@ -169966,7 +170329,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ca_ok$25$next , \xer_ca$24$next } = { \xer_ca_ok$86 , \xer_ca$85 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ca_ok$25$next = 1'h0; @@ -169985,7 +170348,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_ov_ok$27$next , \xer_ov$26$next } = { \xer_ov_ok$88 , \xer_ov$87 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ov_ok$27$next = 1'h0; @@ -170004,7 +170367,7 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o 2'b1?: { \xer_so_ok$29$next , \xer_so$28$next } = { \xer_so_ok$90 , \xer_so$89 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_so_ok$29$next = 1'h0; @@ -170037,9 +170400,9 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$51 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) input [3:0] cr_a; @@ -170969,7 +171332,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -171016,7 +171379,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \sr_op__insn$18$next , \sr_op__is_signed$17$next , \sr_op__is_32bit$16$next , \sr_op__output_cr$15$next , \sr_op__input_cr$14$next , \sr_op__output_carry$13$next , \sr_op__input_carry$12$next , \sr_op__invert_in$11$next , \sr_op__write_cr0$10$next , \sr_op__oe__ok$9$next , \sr_op__oe__oe$8$next , \sr_op__rc__ok$7$next , \sr_op__rc__rc$6$next , \sr_op__imm_data__ok$5$next , \sr_op__imm_data__data$4$next , \sr_op__fn_unit$3$next , \sr_op__insn_type$2$next } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -171042,7 +171405,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \o_ok$20$next , \o$19$next } = { \o_ok$72 , \o$71 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$20$next = 1'h0; @@ -171061,7 +171424,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \cr_a_ok$22$next , \cr_a$21$next } = { \cr_a_ok$74 , \cr_a$73 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$22$next = 1'h0; @@ -171080,7 +171443,7 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, 2'b1?: { \xer_ca_ok$24$next , \xer_ca$23$next } = { \xer_ca_ok$76 , \xer_ca$75 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ca_ok$24$next = 1'h0; @@ -171110,9 +171473,9 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$26 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) input [63:0] fast1; @@ -171917,7 +172280,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -171970,7 +172333,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \o_ok$next , \o$next } = { \o_ok$39 , \o$38 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -171989,7 +172352,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \fast1_ok$next , \fast1$11$next } = { \fast1_ok$41 , \fast1$40 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \fast1_ok$next = 1'h0; @@ -172008,7 +172371,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \fast2_ok$next , \fast2$12$next } = { \fast2_ok$43 , \fast2$42 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \fast2_ok$next = 1'h0; @@ -172027,7 +172390,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \nia_ok$next , \nia$next } = { \nia_ok$45 , \nia$44 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \nia_ok$next = 1'h0; @@ -172046,7 +172409,7 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, 2'b1?: { \msr_ok$next , \msr$next } = { \msr_ok$47 , \msr$46 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \msr_ok$next = 1'h0; @@ -172078,9 +172441,9 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output [3:0] cr_a; @@ -173409,7 +173772,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \o_ok$next , \o$next } = { \o_ok$96 , \o$95 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \o_ok$next = 1'h0; @@ -173428,7 +173791,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \cr_a_ok$next , \cr_a$next } = { \cr_a_ok$98 , \cr_a$97 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cr_a_ok$next = 1'h0; @@ -173447,7 +173810,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \xer_ov_ok$next , \xer_ov$next } = { \xer_ov_ok$100 , \xer_ov$99 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_ov_ok$next = 1'h0; @@ -173466,7 +173829,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \xer_so_ok$next , \xer_so$20$next } = { \xer_so_ok$102 , \xer_so$101 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \xer_so_ok$next = 1'h0; @@ -173484,7 +173847,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -173532,7 +173895,7 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type 2'b1?: { \logical_op__insn$19$next , \logical_op__data_len$18$next , \logical_op__is_signed$17$next , \logical_op__is_32bit$16$next , \logical_op__output_carry$15$next , \logical_op__write_cr0$14$next , \logical_op__invert_out$13$next , \logical_op__input_carry$12$next , \logical_op__zero_a$11$next , \logical_op__invert_in$10$next , \logical_op__oe__ok$9$next , \logical_op__oe__oe$8$next , \logical_op__rc__ok$7$next , \logical_op__rc__rc$6$next , \logical_op__imm_data__ok$5$next , \logical_op__imm_data__data$4$next , \logical_op__fn_unit$3$next , \logical_op__insn_type$2$next } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -173595,9 +173958,9 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn wire \$63 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) input div_by_zero; @@ -174250,7 +174613,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn always @* begin if (\initial ) begin end \saved_state_q_bits_known$next = div_state_next_o_q_bits_known; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \saved_state_q_bits_known$next = 7'h00; @@ -174259,7 +174622,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn always @* begin if (\initial ) begin end \saved_state_dividend_quotient$next = div_state_next_o_dividend_quotient; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \saved_state_dividend_quotient$next = 128'h00000000000000000000000000000000; @@ -174267,6 +174630,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174279,6 +174643,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174291,6 +174656,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174304,6 +174670,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn always @* begin if (\initial ) begin end \empty$next = empty; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *) casez (empty) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" */ @@ -174323,7 +174690,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn \empty$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \empty$next = 1'h1; @@ -174375,7 +174742,7 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn { \logical_op__insn$46$next , \logical_op__data_len$45$next , \logical_op__is_signed$44$next , \logical_op__is_32bit$43$next , \logical_op__output_carry$42$next , \logical_op__write_cr0$41$next , \logical_op__invert_out$40$next , \logical_op__input_carry$39$next , \logical_op__zero_a$38$next , \logical_op__invert_in$37$next , \logical_op__oe__ok$36$next , \logical_op__oe__oe$35$next , \logical_op__rc__ok$34$next , \logical_op__rc__rc$33$next , \logical_op__imm_data__ok$32$next , \logical_op__imm_data__data$31$next , \logical_op__fn_unit$30$next , \logical_op__insn_type$29$next } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type }; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -174576,9 +174943,9 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) output div_by_zero; @@ -175987,7 +176354,7 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty 2'b1?: \r_busy$next = 1'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r_busy$next = 1'h0; @@ -176035,7 +176402,7 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty 2'b1?: { \logical_op__insn$next , \logical_op__data_len$next , \logical_op__is_signed$next , \logical_op__is_32bit$next , \logical_op__output_carry$next , \logical_op__write_cr0$next , \logical_op__invert_out$next , \logical_op__input_carry$next , \logical_op__zero_a$next , \logical_op__invert_in$next , \logical_op__oe__ok$next , \logical_op__oe__oe$next , \logical_op__rc__ok$next , \logical_op__rc__rc$next , \logical_op__imm_data__ok$next , \logical_op__imm_data__data$next , \logical_op__fn_unit$next , \logical_op__insn_type$next } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69 }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -176612,6 +176979,7 @@ module popcount(data_len, o, a); assign \$98 = { 1'h0, pop_2_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 1'h0, pop_2_1 }; always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" *) casez ({ \$192 , \$190 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" */ @@ -177475,9 +177843,9 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest10__data_i; @@ -177591,7 +177959,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src10__data_o$next = 4'h0; @@ -177648,7 +178016,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, 1'h1: \reg$next = w0__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -177688,7 +178056,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src20__data_o$next = 4'h0; @@ -177758,7 +178126,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src30__data_o$next = 4'h0; @@ -177828,7 +178196,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r0__data_o$next = 4'h0; @@ -177898,7 +178266,7 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r20__data_o$next = 4'h0; @@ -177948,9 +178316,9 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest10__data_i; @@ -178062,7 +178430,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src10__data_o$next = 2'h0; @@ -178144,7 +178512,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src20__data_o$next = 2'h0; @@ -178226,7 +178594,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src30__data_o$next = 2'h0; @@ -178308,7 +178676,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r0__data_o$next = 2'h0; @@ -178377,7 +178745,7 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d 1'h1: \reg$next = w0__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -178402,9 +178770,9 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ reg [63:0] \cia0__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia0__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr10__data_i; @@ -178497,7 +178865,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cia0__data_o$next = 64'h0000000000000000; @@ -178579,7 +178947,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \msr0__data_o$next = 64'h0000000000000000; @@ -178661,7 +179029,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \sv0__data_o$next = 64'h0000000000000000; @@ -178730,7 +179098,7 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ 1'h1: \reg$next = d_wr10__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -178752,9 +179120,9 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest11__data_i; @@ -178868,7 +179236,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src11__data_o$next = 4'h0; @@ -178925,7 +179293,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, 1'h1: \reg$next = w1__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -178965,7 +179333,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src21__data_o$next = 4'h0; @@ -179035,7 +179403,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src31__data_o$next = 4'h0; @@ -179105,7 +179473,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r1__data_o$next = 4'h0; @@ -179175,7 +179543,7 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r21__data_o$next = 4'h0; @@ -179225,9 +179593,9 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest11__data_i; @@ -179339,7 +179707,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src11__data_o$next = 2'h0; @@ -179421,7 +179789,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src21__data_o$next = 2'h0; @@ -179503,7 +179871,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src31__data_o$next = 2'h0; @@ -179585,7 +179953,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r1__data_o$next = 2'h0; @@ -179654,7 +180022,7 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d 1'h1: \reg$next = w1__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -179679,9 +180047,9 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ reg [63:0] \cia1__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia1__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr11__data_i; @@ -179774,7 +180142,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cia1__data_o$next = 64'h0000000000000000; @@ -179856,7 +180224,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \msr1__data_o$next = 64'h0000000000000000; @@ -179938,7 +180306,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \sv1__data_o$next = 64'h0000000000000000; @@ -180007,7 +180375,7 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ 1'h1: \reg$next = d_wr11__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -180029,9 +180397,9 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest12__data_i; @@ -180145,7 +180513,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src12__data_o$next = 4'h0; @@ -180202,7 +180570,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, 1'h1: \reg$next = w2__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -180242,7 +180610,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src22__data_o$next = 4'h0; @@ -180312,7 +180680,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src32__data_o$next = 4'h0; @@ -180382,7 +180750,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r2__data_o$next = 4'h0; @@ -180452,7 +180820,7 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r22__data_o$next = 4'h0; @@ -180502,9 +180870,9 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest12__data_i; @@ -180616,7 +180984,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src12__data_o$next = 2'h0; @@ -180698,7 +181066,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src22__data_o$next = 2'h0; @@ -180780,7 +181148,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src32__data_o$next = 2'h0; @@ -180862,7 +181230,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r2__data_o$next = 2'h0; @@ -180931,7 +181299,7 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d 1'h1: \reg$next = w2__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 2'h0; @@ -180956,9 +181324,9 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ reg [63:0] \cia2__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia2__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr12__data_i; @@ -181051,7 +181419,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \cia2__data_o$next = 64'h0000000000000000; @@ -181133,7 +181501,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \msr2__data_o$next = 64'h0000000000000000; @@ -181215,7 +181583,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \sv2__data_o$next = 64'h0000000000000000; @@ -181284,7 +181652,7 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ 1'h1: \reg$next = d_wr12__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 64'h0000000000000000; @@ -181306,9 +181674,9 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest13__data_i; @@ -181422,7 +181790,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src13__data_o$next = 4'h0; @@ -181479,7 +181847,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, 1'h1: \reg$next = w3__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -181519,7 +181887,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src23__data_o$next = 4'h0; @@ -181589,7 +181957,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src33__data_o$next = 4'h0; @@ -181659,7 +182027,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r3__data_o$next = 4'h0; @@ -181729,7 +182097,7 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r23__data_o$next = 4'h0; @@ -181781,9 +182149,9 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest14__data_i; @@ -181897,7 +182265,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src14__data_o$next = 4'h0; @@ -181954,7 +182322,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, 1'h1: \reg$next = w4__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -181994,7 +182362,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src24__data_o$next = 4'h0; @@ -182064,7 +182432,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src34__data_o$next = 4'h0; @@ -182134,7 +182502,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r4__data_o$next = 4'h0; @@ -182204,7 +182572,7 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r24__data_o$next = 4'h0; @@ -182256,9 +182624,9 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest15__data_i; @@ -182372,7 +182740,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src15__data_o$next = 4'h0; @@ -182429,7 +182797,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, 1'h1: \reg$next = w5__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -182469,7 +182837,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src25__data_o$next = 4'h0; @@ -182539,7 +182907,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src35__data_o$next = 4'h0; @@ -182609,7 +182977,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r5__data_o$next = 4'h0; @@ -182679,7 +183047,7 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r25__data_o$next = 4'h0; @@ -182731,9 +183099,9 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest16__data_i; @@ -182847,7 +183215,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src16__data_o$next = 4'h0; @@ -182904,7 +183272,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, 1'h1: \reg$next = w6__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -182944,7 +183312,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src26__data_o$next = 4'h0; @@ -183014,7 +183382,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src36__data_o$next = 4'h0; @@ -183084,7 +183452,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r6__data_o$next = 4'h0; @@ -183154,7 +183522,7 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r26__data_o$next = 4'h0; @@ -183206,9 +183574,9 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest17__data_i; @@ -183322,7 +183690,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src17__data_o$next = 4'h0; @@ -183379,7 +183747,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, 1'h1: \reg$next = w7__data_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \reg$next = 4'h0; @@ -183419,7 +183787,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src27__data_o$next = 4'h0; @@ -183489,7 +183857,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src37__data_o$next = 4'h0; @@ -183559,7 +183927,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r7__data_o$next = 4'h0; @@ -183629,7 +183997,7 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, endcase end endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \r27__data_o$next = 4'h0; @@ -183687,9 +184055,9 @@ module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -183718,7 +184086,7 @@ module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -183749,9 +184117,9 @@ module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -183780,7 +184148,7 @@ module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -183811,9 +184179,9 @@ module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -183842,7 +184210,7 @@ module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -183873,9 +184241,9 @@ module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -183904,7 +184272,7 @@ module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -183935,9 +184303,9 @@ module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -183966,7 +184334,7 @@ module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -183997,9 +184365,9 @@ module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -184028,7 +184396,7 @@ module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -184059,9 +184427,9 @@ module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [1:0] q_int = 2'h0; @@ -184090,7 +184458,7 @@ module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 2'h0; @@ -184121,9 +184489,9 @@ module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -184152,7 +184520,7 @@ module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -184183,9 +184551,9 @@ module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -184214,7 +184582,7 @@ module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -184239,9 +184607,9 @@ module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -184267,7 +184635,7 @@ module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -184292,9 +184660,9 @@ module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -184320,7 +184688,7 @@ module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -184942,9 +185310,9 @@ module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -184973,7 +185341,7 @@ module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185004,9 +185372,9 @@ module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185035,7 +185403,7 @@ module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185066,9 +185434,9 @@ module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185097,7 +185465,7 @@ module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185128,9 +185496,9 @@ module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185159,7 +185527,7 @@ module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185190,9 +185558,9 @@ module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185221,7 +185589,7 @@ module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185252,9 +185620,9 @@ module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185283,7 +185651,7 @@ module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185314,9 +185682,9 @@ module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185345,7 +185713,7 @@ module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185376,9 +185744,9 @@ module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185407,7 +185775,7 @@ module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185438,9 +185806,9 @@ module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185469,7 +185837,7 @@ module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185685,6 +186053,7 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ ); always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" *) casez ({ sign_ext_rs, is_32bit }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" */ @@ -185710,6 +186079,7 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) casez (\$27 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" */ @@ -185722,6 +186092,7 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) casez (\$38 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" */ @@ -185734,7 +186105,7 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ end always @* begin if (\initial ) begin end - result_o = 64'h0000000000000000; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" *) casez (output_mode) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:169" */ @@ -185754,6 +186125,7 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ always @* begin if (\initial ) begin end carry_out_o = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" *) casez (output_mode) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:169" */ @@ -185772,6 +186144,7 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" *) casez (right_shift) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" */ @@ -185784,12 +186157,14 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" *) casez ({ right_shift, clear_left }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" */ 2'b?1: begin \mb$8 = \$9 ; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" *) casez (is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" */ @@ -185818,6 +186193,7 @@ module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_ end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" *) casez ({ \$18 , \$14 }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" */ @@ -185882,9 +186258,9 @@ module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185913,7 +186289,7 @@ module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -185944,9 +186320,9 @@ module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -185975,7 +186351,7 @@ module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186006,9 +186382,9 @@ module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186037,7 +186413,7 @@ module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186068,9 +186444,9 @@ module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186099,7 +186475,7 @@ module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186130,9 +186506,9 @@ module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186161,7 +186537,7 @@ module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186192,9 +186568,9 @@ module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186223,7 +186599,7 @@ module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186254,9 +186630,9 @@ module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186285,7 +186661,7 @@ module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186316,9 +186692,9 @@ module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186347,7 +186723,7 @@ module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186378,9 +186754,9 @@ module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186409,7 +186785,7 @@ module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186440,9 +186816,9 @@ module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -186471,7 +186847,7 @@ module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -186866,6 +187242,7 @@ module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_d /* \nmigen.decoding = "OP_DIVE/30" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" */ 7'h1e: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" *) casez (logical_op__is_32bit) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" */ @@ -187241,9 +187618,9 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) output cr_a_ok; @@ -187774,7 +188151,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -187783,7 +188160,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$64 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -187792,7 +188169,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -187801,7 +188178,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -187810,7 +188187,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -187819,7 +188196,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -187828,7 +188205,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 5'h00; @@ -187837,7 +188214,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 5'h1f; @@ -187846,7 +188223,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \req_l_s_req$next = \$66 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 3'h0; @@ -187855,7 +188232,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \req_l_r_req$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 3'h7; @@ -187886,7 +188263,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \alu_shift_rot0_sr_op__insn$next , \alu_shift_rot0_sr_op__is_signed$next , \alu_shift_rot0_sr_op__is_32bit$next , \alu_shift_rot0_sr_op__output_cr$next , \alu_shift_rot0_sr_op__input_cr$next , \alu_shift_rot0_sr_op__output_carry$next , \alu_shift_rot0_sr_op__input_carry$next , \alu_shift_rot0_sr_op__invert_in$next , \alu_shift_rot0_sr_op__write_cr0$next , \alu_shift_rot0_sr_op__oe__ok$next , \alu_shift_rot0_sr_op__oe__oe$next , \alu_shift_rot0_sr_op__rc__ok$next , \alu_shift_rot0_sr_op__rc__rc$next , \alu_shift_rot0_sr_op__imm_data__ok$next , \alu_shift_rot0_sr_op__imm_data__data$next , \alu_shift_rot0_sr_op__fn_unit$next , \alu_shift_rot0_sr_op__insn_type$next } = { oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: begin @@ -187915,7 +188292,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -187937,7 +188314,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r1__cr_a_ok$next , \data_r1__cr_a$next } = 5'h00; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__cr_a_ok$next = 1'h0; @@ -187959,7 +188336,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif 1'h1: { \data_r2__xer_ca_ok$next , \data_r2__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__xer_ca_ok$next = 1'h0; @@ -188018,7 +188395,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$90 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -188027,7 +188404,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$92 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -188066,7 +188443,7 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif always @* begin if (\initial ) begin end \prev_wr_go$next = \$20 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 3'h0; @@ -188110,9 +188487,9 @@ endmodule (* generator = "nMigen" *) module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *) wire [3:0] memory_r_addr; @@ -188166,7 +188543,7 @@ module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr always @* begin if (\initial ) begin end \ren_delay$next = spr1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$next = 1'h0; @@ -188500,9 +188877,9 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -189033,7 +189410,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -189042,7 +189419,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$68 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -189051,7 +189428,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -189060,7 +189437,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -189069,7 +189446,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -189078,7 +189455,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -189087,7 +189464,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 6'h00; @@ -189096,7 +189473,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 6'h3f; @@ -189105,7 +189482,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \req_l_s_req$next = \$70 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 6'h00; @@ -189114,7 +189491,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \req_l_r_req$next = \$72 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 6'h3f; @@ -189149,7 +189526,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -189171,7 +189548,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r1__spr1_ok$next , \data_r1__spr1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__spr1_ok$next = 1'h0; @@ -189193,7 +189570,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r2__fast1_ok$next , \data_r2__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__fast1_ok$next = 1'h0; @@ -189215,7 +189592,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r3__xer_so_ok$next , \data_r3__xer_so$next } = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r3__xer_so_ok$next = 1'h0; @@ -189237,7 +189614,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r4__xer_ov_ok$next , \data_r4__xer_ov$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r4__xer_ov_ok$next = 1'h0; @@ -189259,7 +189636,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, 1'h1: { \data_r5__xer_ca_ok$next , \data_r5__xer_ca$next } = 3'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r5__xer_ca_ok$next = 1'h0; @@ -189328,7 +189705,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$98 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -189337,7 +189714,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$100 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -189406,7 +189783,7 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, always @* begin if (\initial ) begin end \prev_wr_go$next = \$24 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 6'h00; @@ -189744,6 +190121,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* \nmigen.decoding = "OP_MTSPR/49" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ 7'h31: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) casez (spr) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ @@ -189770,6 +190148,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b 7'h2e: begin o_ok = 1'h1; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:85" *) casez (spr) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:88" */ @@ -189957,6 +190336,7 @@ module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32b /* \nmigen.decoding = "OP_MTSPR/49" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" */ 7'h31: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *) casez (spr) /* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:60" */ @@ -192933,9 +193313,9 @@ module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -192964,7 +193344,7 @@ module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -192995,9 +193375,9 @@ module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -193026,7 +193406,7 @@ module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -193057,9 +193437,9 @@ module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193088,7 +193468,7 @@ module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193119,9 +193499,9 @@ module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -193150,7 +193530,7 @@ module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 5'h00; @@ -193181,9 +193561,9 @@ module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193212,7 +193592,7 @@ module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193243,9 +193623,9 @@ module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193274,7 +193654,7 @@ module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193305,9 +193685,9 @@ module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -193336,7 +193716,7 @@ module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 4'h0; @@ -193367,9 +193747,9 @@ module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193398,7 +193778,7 @@ module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193429,9 +193809,9 @@ module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -193460,7 +193840,7 @@ module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 6'h00; @@ -193491,9 +193871,9 @@ module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -193522,7 +193902,7 @@ module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 3'h0; @@ -193553,9 +193933,9 @@ module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -193584,7 +193964,7 @@ module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_c always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -193615,9 +193995,9 @@ module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -193646,7 +194026,7 @@ module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -193684,9 +194064,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data reg [63:0] cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] data_i; @@ -193882,7 +194262,7 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end \ren_delay$19$next = sv__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$19$next = 3'h0; @@ -193901,7 +194281,7 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end \ren_delay$next = cia__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$next = 3'h0; @@ -193920,7 +194300,7 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data always @* begin if (\initial ) begin end \ren_delay$12$next = msr__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$12$next = 3'h0; @@ -193977,9 +194357,9 @@ module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -194008,7 +194388,7 @@ module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -194033,7 +194413,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input TAP_bus__tms; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *) input core_bigendian_i; @@ -194381,7 +194761,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input pc_i_ok; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *) output [63:0] pc_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -194667,7 +195047,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) wire ti_coresync_clk; ti ti ( .TAP_bus__tck(TAP_bus__tck), @@ -194990,17 +195370,17 @@ endmodule (* generator = "nMigen" *) module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__cyc, jtag_wb__we, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$100 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) + wire \$102 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) - wire [64:0] \$102 ; + wire [64:0] \$104 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) - wire [64:0] \$103 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) - wire \$105 ; + wire [64:0] \$105 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) wire [31:0] \$107 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) wire [6:0] \$108 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *) wire [31:0] \$111 ; @@ -195008,191 +195388,191 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [64:0] \$112 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) wire [64:0] \$113 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) wire [6:0] \$115 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$122 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$124 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$126 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) - wire \$128 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$128 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) wire \$130 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$134 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) wire [7:0] \$136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) wire [7:0] \$137 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) wire [7:0] \$139 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) wire [7:0] \$140 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$142 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$144 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$146 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$148 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$150 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$156 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) wire \$158 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$160 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$162 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) - wire \$164 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$164 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) wire \$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$168 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$170 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$172 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$174 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$176 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$178 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$180 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$182 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$184 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$186 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$188 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$190 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$192 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$194 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$196 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$198 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$200 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$202 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$204 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$206 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) wire \$208 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) wire [2:0] \$209 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$212 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$214 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$216 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$218 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$220 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) - wire \$222 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$222 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) wire \$224 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$228 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) wire \$23 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$230 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$232 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$234 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$236 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$238 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$240 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) wire \$242 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) wire [2:0] \$243 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$246 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$248 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:849" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) wire \$25 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) wire \$250 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$252 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$256 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$258 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$260 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$262 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:688" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *) wire \$264 ; - (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) wire [63:0] \$266 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) wire \$268 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) wire [2:0] \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) wire \$270 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) wire \$272 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] \$274 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] \$276 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) wire [64:0] \$278 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) wire [64:0] \$279 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) wire [2:0] \$28 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) wire [64:0] \$281 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) wire [64:0] \$282 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) wire \$32 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) wire \$34 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$36 ; @@ -195216,47 +195596,47 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [63:0] \$54 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) - wire \$72 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$72 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) wire \$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) wire \$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) wire \$92 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) - wire \$94 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + wire \$94 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) wire \$96 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) wire \$98 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -195268,7 +195648,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db input TAP_bus__tms; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *) reg [7:0] core_asmcode = 8'h00; @@ -195638,7 +196018,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg [2:0] \core_core_xer_in$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *) wire core_corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) wire core_coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) reg core_cr_out_ok = 1'h0; @@ -195738,7 +196118,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg core_sv_a_nz = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *) reg \core_sv_a_nz$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) wire core_wb_dcache_en; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) reg [2:0] core_wen; @@ -195748,7 +196128,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg core_xer_out = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) reg \core_xer_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg cu_st__rel_o_dly = 1'h0; @@ -195780,17 +196160,17 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg [6:0] cur_cur_vl = 7'h00; (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) reg [6:0] \cur_cur_vl$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1022" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) reg d_cr_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1022" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) reg \d_cr_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1012" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) reg d_reg_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1012" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *) reg \d_reg_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) reg d_xer_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *) reg \d_xer_delay$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) wire [6:0] dbg_core_dbg_core_dbg_dststep; @@ -196338,9 +196718,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [2:0] dec2_xer_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *) wire dec2_xer_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:848" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) reg [1:0] delay = 2'h3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:848" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) reg [1:0] \delay$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output eint_0__core__i; @@ -196354,33 +196734,33 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db output eint_2__core__i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input eint_2__pad__i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) reg exec_fsm_state = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) reg \exec_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" *) reg exec_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:945" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955" *) reg exec_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960" *) reg exec_pc_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959" *) reg exec_pc_valid_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) reg [1:0] fetch_fsm_state = 2'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) reg [1:0] \fetch_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:934" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:944" *) reg fetch_insn_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:933" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) reg fetch_insn_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" *) reg fetch_pc_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:929" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939" *) reg fetch_pc_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) reg [1:0] fsm_state = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) reg [1:0] \fsm_state$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output gpio_e10__core__i; @@ -196628,19 +197008,19 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [63:0] imem_f_instr_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" *) reg imem_f_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) wire imem_wb_icache_en; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268" *) reg insn_done; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) input [15:0] int_level_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:686" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:698" *) reg is_last; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:923" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:933" *) wire is_svp64_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) reg [2:0] issue_fsm_state = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) reg [2:0] \issue_fsm_state$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) reg jtag_dmi0__ack_o = 1'h0; @@ -196710,7 +197090,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db output mtwi_sda__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mtwi_sda__pad__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1065" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *) reg [63:0] new_dec; (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *) reg [6:0] new_svstate_dststep; @@ -196724,21 +197104,21 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg [1:0] new_svstate_svstep; (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *) reg [6:0] new_svstate_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1082" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1096" *) reg [63:0] new_tb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) wire [6:0] next_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" *) wire [6:0] next_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:910" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *) reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:910" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *) reg [63:0] \nia$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) reg [63:0] pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:889" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *) reg pc_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:889" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *) reg \pc_changed$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) input [63:0] pc_i; @@ -196750,17 +197130,17 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg pc_ok_delay = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg \pc_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:842" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) wire por_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" *) wire pred_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" *) reg pred_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952" *) reg pred_mask_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:941" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" *) wire pred_mask_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -197046,9 +197426,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db input sdr_we_n__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output sdr_we_n__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:890" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *) reg sv_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:890" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *) reg \sv_changed$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *) reg [63:0] svstate; @@ -197060,9 +197440,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db reg svstate_ok_delay = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg \svstate_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:847" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) wire ti_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) reg update_svstate; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) wire xics_icp_core_irq_o; @@ -197074,101 +197454,101 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db wire [7:0] xics_ics_icp_o_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) wire [3:0] xics_ics_icp_o_src; - assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last; - assign \$103 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) 3'h4; - assign \$105 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; - assign \$108 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *) 6'h20; + assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; + assign \$105 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) 3'h4; + assign \$108 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$107 = imem_f_instr_o >> \$108 ; assign \$113 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) 3'h4; - assign \$115 = \$112 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *) 6'h20; + assign \$115 = \$112 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$111 = imem_f_instr_o >> \$115 ; - assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$120 ; - assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$126 ; - assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed; - assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) 1'h0; - assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last; - assign \$137 = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" *) 1'h1; - assign \$140 = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" *) 1'h1; - assign \$142 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$146 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$144 ; - assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$150 ; - assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0; - assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$154 ; - assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *) is_svp64_mode; - assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$162 ; - assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed; - assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) 1'h0; - assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last; - assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$174 ; - assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$180 ; - assign \$184 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$188 = \$184 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$186 ; - assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$192 ; - assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$198 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$200 = \$196 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$198 ; - assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$204 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$206 = \$202 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$204 ; - assign \$209 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) 1'h1; + assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$120 ; + assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$126 ; + assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$137 = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) 1'h1; + assign \$140 = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) 1'h1; + assign \$142 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$144 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$146 = \$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$144 ; + assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$150 ; + assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$154 ; + assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) is_svp64_mode; + assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$162 ; + assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$174 ; + assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$180 ; + assign \$184 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$188 = \$184 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$186 ; + assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$192 ; + assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$198 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$200 = \$196 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$198 ; + assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$204 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$206 = \$202 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$204 ; + assign \$209 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) 1'h1; assign \$208 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$209 ; - assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$214 ; - assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$220 ; - assign \$224 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed; - assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) 1'h0; - assign \$228 = \$226 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last; - assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$232 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$234 = \$230 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$232 ; - assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; + assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$214 ; + assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$220 ; + assign \$224 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$228 = \$226 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$232 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$234 = \$230 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$232 ; + assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read; - assign \$240 = \$236 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$238 ; - assign \$243 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) 3'h4; + assign \$240 = \$236 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$238 ; + assign \$243 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) 3'h4; assign \$242 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$243 ; - assign \$246 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0; - assign \$248 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$246 ; - assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) core_corebusy_o; - assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$256 = \$252 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$254 ; - assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:849" *) 1'h0; - assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$262 = \$258 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$260 ; - assign \$264 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:688" *) cur_cur_vl; - assign \$266 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; - assign \$268 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) 7'h01; - assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) core_corebusy_o; - assign \$272 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) core_corebusy_o; + assign \$246 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$248 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$246 ; + assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; + assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$256 = \$252 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$254 ; + assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) 1'h0; + assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$262 = \$258 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$260 ; + assign \$264 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *) cur_cur_vl; + assign \$266 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; + assign \$268 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) 7'h01; + assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; + assign \$272 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o; assign \$274 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o; assign \$276 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o; - assign \$279 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) 1'h1; - assign \$282 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083" *) 1'h1; - assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850" *) 1'h1; - assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) dbg_core_rst_o; - assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) rst; - assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) \$32 ; + assign \$279 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) 1'h1; + assign \$282 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) 1'h1; + assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) 1'h1; + assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) dbg_core_rst_o; + assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) rst; + assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) \$32 ; assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly; assign \$38 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$36 ; assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; @@ -197180,27 +197560,27 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db assign \$52 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; assign \$54 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) svstate_i; assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst; - assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$60 ; - assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0; - assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$64 ; - assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$70 ; - assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed; - assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) 1'h0; - assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last; - assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o; - assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst; - assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$82 ; - assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0; - assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$86 ; - assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o; - assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst; - assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$92 ; - assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed; - assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) 1'h0; + assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$60 ; + assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$64 ; + assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$70 ; + assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; + assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last; + assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o; + assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst; + assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$82 ; + assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0; + assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$86 ; + assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o; + assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst; + assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$92 ; + assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed; + assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0; always @(posedge clk) fsm_state <= \fsm_state$next ; always @(posedge clk) @@ -197371,12 +197751,12 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db issue_fsm_state <= \issue_fsm_state$next ; always @(posedge clk) dec2_raw_opcode_in <= \dec2_raw_opcode_in$next ; + always @(posedge clk) + nia <= \nia$next ; always @(posedge clk) fetch_fsm_state <= \fetch_fsm_state$next ; always @(posedge clk) msr_read <= \msr_read$next ; - always @(posedge clk) - nia <= \nia$next ; always @(posedge clk) svstate_ok_delay <= \svstate_ok_delay$next ; always @(posedge clk) @@ -197941,7 +198321,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_addr_i$next = jtag_dmi0__addr_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dbg_dmi_addr_i$next = 4'h0; @@ -197950,7 +198330,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_req_i$next = jtag_dmi0__req_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dbg_dmi_req_i$next = 1'h0; @@ -197968,34 +198348,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \core_core_srcstep$next = core_core_srcstep; \core_core_vl$next = core_core_vl; \core_core_maxvl$next = core_core_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: { \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_msr$next , \core_core_pc$next } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: begin @@ -198015,34 +198395,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_raw_insn_i$next = core_raw_insn_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: \core_raw_insn_i$next = dec2_raw_opcode_in; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \core_raw_insn_i$next = 32'd0; @@ -198051,34 +198431,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_bigendian_i$10$next = \core_bigendian_i$10 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: \core_bigendian_i$10$next = core_bigendian_i; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \core_bigendian_i$10$next = 1'h0; @@ -198087,34 +198467,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_sv_a_nz$next = core_sv_a_nz; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: \core_sv_a_nz$next = dec2_sv_a_nz; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \core_sv_a_nz$next = 1'h0; @@ -198123,34 +198503,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end exec_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: exec_insn_valid_i = 1'h1; endcase @@ -198158,42 +198538,43 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end exec_pc_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$256 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: exec_pc_ready_i = 1'h1; endcase @@ -198202,46 +198583,47 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end is_last = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$262 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ 1'h1: is_last = \$264 ; endcase @@ -198251,9 +198633,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_wen$11 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 1'h1: \core_wen$11 = 3'h4; endcase @@ -198261,9 +198643,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_data_i$12 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 1'h1: \core_data_i$12 = \$266 ; endcase @@ -198271,10 +198653,10 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end exec_insn_ready_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: exec_insn_ready_o = 1'h1; endcase @@ -198282,23 +198664,24 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_ivalid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ 1'h1: core_ivalid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) casez (\$268 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" */ 1'h1: core_ivalid_i = 1'h1; endcase @@ -198307,14 +198690,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ 1'h1: core_issue_i = 1'h1; endcase @@ -198323,33 +198706,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \exec_fsm_state$next = exec_fsm_state; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ 1'h1: \exec_fsm_state$next = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) casez (\$270 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */ 1'h1: \exec_fsm_state$next = 1'h0; endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \exec_fsm_state$next = 1'h0; @@ -198358,18 +198742,19 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end exec_pc_valid_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) casez (\$272 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ 1'h1: exec_pc_valid_o = 1'h1; endcase @@ -198378,9 +198763,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_dmi__addr = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1004" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1004" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */ 1'h1: core_dmi__addr = dbg_d_gpr_addr[4:0]; endcase @@ -198388,9 +198773,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_dmi__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1004" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1004" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */ 1'h1: core_dmi__ren = 1'h1; endcase @@ -198398,7 +198783,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \d_reg_delay$next = dbg_d_gpr_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \d_reg_delay$next = 1'h0; @@ -198407,9 +198792,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_gpr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1014" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1014" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */ 1'h1: dbg_d_gpr_data = core_dmi__data_o; endcase @@ -198417,9 +198802,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_gpr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1014" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1014" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */ 1'h1: dbg_d_gpr_ack = 1'h1; endcase @@ -198427,9 +198812,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_full_rd2__ren = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *) casez (dbg_d_cr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" */ 1'h1: core_full_rd2__ren = 8'hff; endcase @@ -198437,7 +198822,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \d_cr_delay$next = dbg_d_cr_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \d_cr_delay$next = 1'h0; @@ -198446,9 +198831,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_cr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */ 1'h1: dbg_d_cr_data = \$274 ; endcase @@ -198456,9 +198841,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_cr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */ 1'h1: dbg_d_cr_ack = 1'h1; endcase @@ -198466,9 +198851,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_full_rd__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1030" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *) casez (dbg_d_xer_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1030" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" */ 1'h1: core_full_rd__ren = 3'h7; endcase @@ -198476,7 +198861,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \d_xer_delay$next = dbg_d_xer_req; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \d_xer_delay$next = 1'h0; @@ -198485,9 +198870,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_xer_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */ 1'h1: dbg_d_xer_data = \$276 ; endcase @@ -198495,9 +198880,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_d_xer_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */ 1'h1: dbg_d_xer_ack = 1'h1; endcase @@ -198505,18 +198890,18 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue__addr = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: core_issue__addr = 3'h6; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1075" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ 2'h2: core_issue__addr = 3'h7; endcase @@ -198524,45 +198909,45 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: core_issue__ren = 1'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1075" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ 2'h2: core_issue__ren = 1'h1; endcase end always @* begin if (\initial ) begin end - \fsm_state$next = fsm_state; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: \fsm_state$next = 2'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: \fsm_state$next = 2'h2; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1075" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ 2'h2: \fsm_state$next = 2'h3; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ 2'h3: \fsm_state$next = 2'h0; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \fsm_state$next = 2'h0; @@ -198571,14 +198956,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end new_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: new_dec = \$278 [63:0]; endcase @@ -198586,22 +198971,23 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \core_issue__addr$13 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: \core_issue__addr$13 = 3'h6; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1075" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ 2'h3: \core_issue__addr$13 = 3'h7; endcase @@ -198609,22 +198995,23 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue__wen = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: core_issue__wen = 1'h1; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1075" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ 2'h3: core_issue__wen = 1'h1; endcase @@ -198632,22 +199019,23 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_issue__data_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: core_issue__data_i = new_dec; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1075" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ 2'h3: core_issue__data_i = new_tb; endcase @@ -198655,22 +199043,23 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end new_tb = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1075" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ 2'h3: new_tb = \$281 [63:0]; endcase @@ -198687,9 +199076,9 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \cur_cur_vl$next = cur_cur_vl; \cur_cur_maxvl$next = cur_cur_maxvl; \dec2_cur_eint$next = xics_icp_core_irq_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" *) casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" */ 1'h1: { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000; endcase @@ -198717,24 +199106,24 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \dec2_cur_msr$next = core_msr__data_o; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 1'h1: { \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1058" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1064" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */ 2'h1: \dec2_cur_dec$next = new_dec; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: begin @@ -198754,7 +199143,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_we_i$next = jtag_dmi0__we_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dbg_dmi_we_i$next = 1'h0; @@ -198769,7 +199158,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db 1'h1: \pc_ok_delay$next = \$42 ; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \pc_ok_delay$next = 1'h0; @@ -198778,7 +199167,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \dbg_dmi_din$next = jtag_dmi0__din; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \dbg_dmi_din$next = 64'h0000000000000000; @@ -198814,6 +199203,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db casez (\$46 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) casez (pc_i_ok) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ @@ -198834,7 +199224,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db 1'h1: \svstate_ok_delay$next = \$50 ; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \svstate_ok_delay$next = 1'h0; @@ -198870,6 +199260,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db casez (\$56 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) casez (svstate_i_ok) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" */ @@ -198884,85 +199275,88 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_wen = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$62 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) casez (\$66 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$72 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) casez ({ \$78 , \$74 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ 2'b1?: core_wen = 3'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ 1'h1: core_wen = 3'h1; endcase @@ -198972,85 +199366,88 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_data_i = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$84 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ 1'h1: core_data_i = pc_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) casez (\$88 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ 1'h1: core_data_i = nia; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$94 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) casez ({ \$100 , \$96 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ 2'b1?: core_data_i = nia; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ 1'h1: core_data_i = pc_i; endcase @@ -199073,44 +199470,10 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db endcase endcase end - always @* begin - if (\initial ) begin end - \nia$next = nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *) - casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" */ - 1'h1: - \nia$next = 64'h0000000000000000; - endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) - casez (fetch_fsm_state) - /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ - 2'h0: - /* empty */; - /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ - 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) - casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ - 1'h1: - /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ - default: - \nia$next = \$102 [63:0]; - endcase - endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) - casez (rst) - 1'h1: - \nia$next = 64'h0000000000000000; - endcase - end always @* begin if (\initial ) begin end \jtag_dmi0__ack_o$next = dbg_dmi_ack_o; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \jtag_dmi0__ack_o$next = 1'h0; @@ -199143,15 +199506,6 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db endcase endcase end - always @* begin - if (\initial ) begin end - \jtag_dmi0__dout$next = dbg_dmi_dout; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) - casez (rst) - 1'h1: - \jtag_dmi0__dout$next = 64'h0000000000000000; - endcase - end always @* begin if (\initial ) begin end imem_a_valid_i = 1'h0; @@ -199186,6 +199540,15 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db endcase endcase end + always @* begin + if (\initial ) begin end + \jtag_dmi0__dout$next = dbg_dmi_dout; + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \jtag_dmi0__dout$next = 64'h0000000000000000; + endcase + end always @* begin if (\initial ) begin end imem_f_valid_i = 1'h0; @@ -199238,13 +199601,13 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ 2'h1: (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) - casez (\$105 ) + casez (\$102 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 1'h1: \msr_read$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \msr_read$next = 1'h1; @@ -199253,6 +199616,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \fetch_fsm_state$next = fetch_fsm_state; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ @@ -199267,6 +199631,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db /* \nmigen.decoding = "INSN_READ/1" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ 2'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) casez (imem_f_busy_o) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ @@ -199279,6 +199644,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db /* \nmigen.decoding = "INSN_READ2/3" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ 2'h3: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) casez (imem_f_busy_o) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ @@ -199298,12 +199664,47 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \fetch_fsm_state$next = 2'h0; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \fetch_fsm_state$next = 2'h0; endcase end + always @* begin + if (\initial ) begin end + \nia$next = nia; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) + casez (fetch_fsm_state) + /* \nmigen.decoding = "IDLE/0" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" */ + 2'h0: + /* empty */; + /* \nmigen.decoding = "INSN_READ/1" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ + 2'h1: + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) + casez (imem_f_busy_o) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ + 1'h1: + /* empty */; + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" */ + default: + \nia$next = \$104 [63:0]; + endcase + endcase + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" *) + casez (core_coresync_rst) + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" */ + 1'h1: + \nia$next = 64'h0000000000000000; + endcase + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) + casez (rst) + 1'h1: + \nia$next = 64'h0000000000000000; + endcase + end always @* begin if (\initial ) begin end \dec2_raw_opcode_in$next = dec2_raw_opcode_in; @@ -199316,6 +199717,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db /* \nmigen.decoding = "INSN_READ/1" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" */ 2'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *) casez (imem_f_busy_o) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" */ @@ -199328,6 +199730,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db /* \nmigen.decoding = "INSN_READ2/3" */ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" */ 2'h3: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *) casez (imem_f_busy_o) /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ @@ -199342,6 +199745,7 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end fetch_insn_valid_o = 1'h0; + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ @@ -199365,72 +199769,76 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep }; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$122 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$128 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) casez ({ \$134 , \$130 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ 2'b1?: begin new_svstate_srcstep = 7'h00; new_svstate_dststep = 7'h00; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:720" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ default: begin new_svstate_srcstep = next_srcstep; @@ -199438,11 +199846,11 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db end endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase @@ -199452,14 +199860,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end fetch_pc_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$146 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: fetch_pc_valid_i = 1'h1; endcase @@ -199468,106 +199876,109 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \issue_fsm_state$next = issue_fsm_state; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$152 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" *) casez (fetch_pc_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:561" */ 1'h1: \issue_fsm_state$next = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) casez (\$156 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ 1'h1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:581" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" */ default: \issue_fsm_state$next = 3'h2; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" *) casez (pred_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" */ 1'h1: \issue_fsm_state$next = 3'h4; endcase /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) casez (pred_mask_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" */ 1'h1: \issue_fsm_state$next = 3'h5; endcase /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) casez (\$158 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ 1'h1: \issue_fsm_state$next = 3'h2; endcase /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: \issue_fsm_state$next = 3'h6; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" *) casez (exec_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" */ 1'h1: \issue_fsm_state$next = 3'h7; endcase /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$164 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) casez ({ \$170 , \$166 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ 2'b?1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ 2'b1?: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:720" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ default: \issue_fsm_state$next = 3'h5; endcase endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \issue_fsm_state$next = 3'h0; @@ -199576,53 +199987,56 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end core_stopped_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$176 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: core_stopped_i = 1'h1; endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$182 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: core_stopped_i = 1'h1; endcase @@ -199631,53 +200045,56 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end dbg_core_stopped_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$188 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: dbg_core_stopped_i = 1'h1; endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$194 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: dbg_core_stopped_i = 1'h1; endcase @@ -199686,89 +200103,93 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \pc_changed$next = pc_changed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$200 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$206 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ 1'h1: \pc_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) casez (\$208 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \pc_changed$next = 1'h0; @@ -199777,78 +200198,82 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end update_svstate = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$216 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ 1'h1: update_svstate = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$222 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) casez ({ \$228 , \$224 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */ 2'b1?: update_svstate = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:720" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */ default: update_svstate = 1'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 1'h1: update_svstate = 1'h1; endcase @@ -199858,89 +200283,93 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \sv_changed$next = sv_changed; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) casez (\$234 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:678" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) casez (\$240 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ 1'h1: \sv_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) casez (\$242 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \sv_changed$next = 1'h0; @@ -199949,14 +200378,14 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end fetch_insn_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: fetch_insn_ready_i = 1'h1; endcase @@ -199964,43 +200393,44 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end insn_done = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) casez (\$248 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */ 1'h1: insn_done = 1'h1; endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *) + (* full_case = 32'd1 *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:770" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) casez (\$250 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */ 1'h1: insn_done = 1'h1; endcase @@ -200010,18 +200440,18 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end pred_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: pred_insn_valid_i = 1'h1; endcase @@ -200029,22 +200459,22 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end pred_mask_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: pred_mask_ready_i = 1'h1; endcase @@ -200110,34 +200540,34 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db \core_core_core_cr_wr$next = core_core_core_cr_wr; \core_core_cr_wr_ok$next = core_core_cr_wr_ok; \core_core_core_is_32bit$next = core_core_core_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:544" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:566" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */ 3'h2: { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_$signal$9$next , \core_core_core_exc_$signal$8$next , \core_core_core_exc_$signal$7$next , \core_core_core_exc_$signal$6$next , \core_core_core_exc_$signal$5$next , \core_core_core_exc_$signal$4$next , \core_core_core_exc_$signal$3$next , \core_core_core_exc_$signal$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_cia, dec2_msr, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode }; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: begin @@ -200174,15 +200604,15 @@ module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, db always @* begin if (\initial ) begin end \delay$next = delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:849" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) casez (\$25 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:849" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" */ 1'h1: \delay$next = \$27 [1:0]; endcase end assign \$27 = \$28 ; - assign \$102 = \$103 ; + assign \$104 = \$105 ; assign \$112 = \$113 ; assign \$136 = \$137 ; assign \$139 = \$140 ; @@ -200529,9 +200959,9 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -201045,7 +201475,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rok_l_s_rdok$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_s_rdok$next = 1'h0; @@ -201054,7 +201484,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rok_l_r_rdok$next = \$65 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rok_l_r_rdok$next = 1'h1; @@ -201063,7 +201493,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rst_l_s_rst$next = all_rd; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_s_rst$next = 1'h0; @@ -201072,7 +201502,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \rst_l_r_rst$next = rst_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \rst_l_r_rst$next = 1'h1; @@ -201081,7 +201511,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \opc_l_s_opc$next = cu_issue_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_s_opc$next = 1'h0; @@ -201090,7 +201520,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \opc_l_r_opc$next = req_done; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \opc_l_r_opc$next = 1'h1; @@ -201099,7 +201529,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \src_l_s_src$next = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_s_src$next = 4'h0; @@ -201108,7 +201538,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \src_l_r_src$next = reset_r; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \src_l_r_src$next = 4'hf; @@ -201117,7 +201547,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \req_l_s_req$next = \$67 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_s_req$next = 5'h00; @@ -201126,7 +201556,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \req_l_r_req$next = \$69 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \req_l_r_req$next = 5'h1f; @@ -201166,7 +201596,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r0__o_ok$next , \data_r0__o$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r0__o_ok$next = 1'h0; @@ -201188,7 +201618,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r1__fast1_ok$next , \data_r1__fast1$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r1__fast1_ok$next = 1'h0; @@ -201210,7 +201640,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r2__fast2_ok$next , \data_r2__fast2$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r2__fast2_ok$next = 1'h0; @@ -201232,7 +201662,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r3__nia_ok$next , \data_r3__nia$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r3__nia_ok$next = 1'h0; @@ -201254,7 +201684,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni 1'h1: { \data_r4__msr_ok$next , \data_r4__msr$next } = 65'h00000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \data_r4__msr_ok$next = 1'h0; @@ -201303,7 +201733,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \alui_l_r_alui$next = \$89 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alui_l_r_alui$next = 1'h1; @@ -201312,7 +201742,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \alu_l_r_alu$next = \$91 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \alu_l_r_alu$next = 1'h1; @@ -201371,7 +201801,7 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni always @* begin if (\initial ) begin end \prev_wr_go$next = \$21 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \prev_wr_go$next = 5'h00; @@ -201428,9 +201858,9 @@ module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -201459,7 +201889,7 @@ module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -201490,9 +201920,9 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -201521,7 +201951,7 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -201552,9 +201982,9 @@ module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -201583,7 +202013,7 @@ module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); always @* begin if (\initial ) begin end \q_int$next = \$5 ; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \q_int$next = 1'h0; @@ -202109,9 +202539,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] data_i; @@ -202334,7 +202764,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$18$next = src3__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$18$next = 3'h0; @@ -202353,7 +202783,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$next = src1__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$next = 3'h0; @@ -202372,7 +202802,7 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, always @* begin if (\initial ) begin end \ren_delay$11$next = src2__ren; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (coresync_rst) 1'h1: \ren_delay$11$next = 3'h0; @@ -202439,7 +202869,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) output core_irq_o; @@ -202495,7 +202925,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, reg [7:0] min_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *) reg [7:0] pending_priority; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) reg wb_ack = 1'h0; @@ -202550,7 +202980,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, always @* begin if (\initial ) begin end { \wb_ack$next , \wb_rd_data$next , \irq$next , \mfrr$next , \cppr$next , \xisr$next } = { \wb_ack$6 , \wb_rd_data$5 , \irq$4 , \mfrr$3 , \cppr$2 , \xisr$1 }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: begin @@ -202570,6 +203000,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, casez (\$23 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *) casez (icp_wb__we) /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" */ @@ -202601,6 +203032,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, casez (\$27 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *) casez (icp_wb__we) /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" */ @@ -202635,6 +203067,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, end always @* begin if (\initial ) begin end + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) casez (\$31 ) /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" */ @@ -202648,7 +203081,7 @@ module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, always @* begin if (\initial ) begin end \core_irq_o$next = irq; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \core_irq_o$next = 1'h0; @@ -202946,7 +203379,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) reg [3:0] cur_idx0; @@ -203066,7 +203499,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc wire reg_is_debug; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *) wire reg_is_xive; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *) wire wb_valid; @@ -203305,6 +203738,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc casez (reg_is_xive) /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" */ 1'h1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" *) casez (reg_idx) 4'h0: @@ -203342,7 +203776,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc endcase endcase endcase - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: begin @@ -203458,7 +203892,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \int_level_l$next = int_level_i; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \int_level_l$next = 16'h0000; @@ -203671,6 +204105,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc casez ({ reg_is_debug, reg_is_config, reg_is_xive }) /* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" */ 3'b??1: + (* full_case = 32'd1 *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) casez (reg_idx) 4'h0: @@ -203757,7 +204192,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \ics_wb__dat_r$next = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] }; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \ics_wb__dat_r$next = 32'd0; @@ -203766,7 +204201,7 @@ module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc always @* begin if (\initial ) begin end \ics_wb__ack$next = wb_valid; - (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *) + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" *) casez (rst) 1'h1: \ics_wb__ack$next = 1'h0;