From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 1 Jul 2022 08:42:09 +0000 (+0100)
Subject: move image with resize to pdf-suitable location
X-Git-Tag: opf_rfc_ls005_v1~1423
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=110cd04a47ae95ab55aaeaf65ac93f1fa067f1c4;p=libreriscv.git

move image with resize to pdf-suitable location
---

diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex
index cd688458d..2fb766f6c 100644
--- a/openpower/simple_v_spec.tex
+++ b/openpower/simple_v_spec.tex
@@ -4,6 +4,7 @@
 \usepackage{lscape}
 \usepackage{sectsty}
 \usepackage{appendix}
+\usepackage{graphicx}
 \usepackage{anyfontsize}
 \usepackage{ifxetex,ifluatex}
 \usepackage{fixltx2e} % provides \textsubscript
diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 078521720..24f1ec7f4 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -381,6 +381,8 @@ This means that Vector elements start from locations specified by 64 bit
 "register" but that from that location onwards the elements *overlap
 subsequent registers*.
 
+![image](/svp64-primer/img/svp64_regs.svg){ width=40% }
+
 Here is another way to view the same concept, bearing in mind that it
 is assumed a LE memory order:
 
@@ -438,8 +440,6 @@ each element word:
 register number (`RT`, `RA`) indicates the *starting* point for the storage
 and retrieval of the elements.
 
-![image](/svp64-primer/img/svp64_regs.svg)
-
 Our simple loop, instead of accessing the array of regfile entries
 with a computed index `iregs[RT+i]`, would access the appropriate element
 of the appropriate width, such as `iregs[RT].s[i]` in order to access