From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 13:52:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1707
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=110fb56aabebea8e9d8adca25adc5c69a8214e03;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 7f155b479..57eb3f0fc 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -143,7 +143,6 @@ Scalar Instructions:
 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
 * [[sv/fclass]] detect class of FP numbers
 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
-* [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
 * Twin targetted instructions (two registers out, one implicit, just like
   Load-with-Update).