From: lkcl <lkcl@web>
Date: Sun, 27 Dec 2020 04:20:47 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~807
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=111442714ecb1222f2abf200bc51e784fb4972b3;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index db6ed8920..2408836a0 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -276,7 +276,7 @@ The solution comes in terms of rethinking the definition of a Register
 File.  The typical regfile may be considered to be a multi-ported SRAM
 block, 64 bits wide and usually 32 entries deep, to give 32 64 bit
 registers.  Conceptually, to get our variable element width vectors,
-we may think of the regfile as insead being the following c-based data
+we may think of the regfile as instead being the following c-based data
 structure:
 
     typedef union {