From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 06:39:41 +0000 (+0000)
Subject: redirect store insns through sv_proc_t for elwidth adjustment
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=113f1338cd3c37346ae3dd86da7e18dd0bb8ba05;p=riscv-isa-sim.git

redirect store insns through sv_proc_t for elwidth adjustment
---

diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index d038d9a..cd8a3b0 100644
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), ((freg_t)RVC_FRS2S).v[0]);
+MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), ((freg_t)RVC_FRS2S).v[0]); // RVC_RS1S
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 2f03210..988096b 100644
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()), ((freg_t)RVC_FRS2S).v[0]);
+  MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), ((freg_t)RVC_FRS2S).v[0]); //RVC_RS1S
 } else { // c.sd
-  MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), RVC_RS2S);
+  MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), RVC_RS2S); //RVC_RS1S, 
 }
diff --git a/riscv/insns/c_sw.h b/riscv/insns/c_sw.h
index 098b4b4..29b99d4 100644
--- a/riscv/insns/c_sw.h
+++ b/riscv/insns/c_sw.h
@@ -1,2 +1,2 @@
 require_extension('C');
-MMU.store_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()), RVC_RS2S);
+MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), RVC_RS2S); // RVC_RS1S
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 0383806..16b009b 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RS1, insn.s_imm()), ((freg_t)FRS2).v[0]);
+MMU.store_uint64(insn.rs1(), insn.s_imm(), ((freg_t)FRS2).v[0]); // RS1
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index d125246..37fca6a 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(rv_add(RS1, insn.s_imm()), ((freg_t)FRS2).v[0]);
+MMU.store_uint32(insn.rs1(), insn.s_imm(), ((freg_t)FRS2).v[0]); // RS1
diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index ad656cf..0a968d9 100644
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-MMU.store_uint8(rv_add(RS1, insn.s_imm()), RS2);
+MMU.store_uint8(insn.rs1(), insn.s_imm(), RS2); // RS1
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index df56fbe..f92237c 100644
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require_rv64;
-MMU.store_uint64(rv_add(RS1, insn.s_imm()), RS2);
+MMU.store_uint64(insn.rs1(), insn.s_imm(), RS2); // RS1
diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index e216392..13e5786 100644
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-MMU.store_uint16(rv_add(RS1, insn.s_imm()), RS2);
+MMU.store_uint16(insn.rs1(), insn.s_imm(), RS2); // RS1
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index 32c2851..d8a567f 100644
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-MMU.store_uint32(rv_add(RS1, insn.s_imm()), RS2);
+MMU.store_uint32(insn.rs1(), insn.s_imm(), RS2); // RS1