From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 15:09:20 +0000 (+0100)
Subject: comment out wrflag as it should already be in the fu.wr.rel logic
X-Git-Tag: div_pipeline~602
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=114dc57e3e60b89a6a8813dfc6e7b0d3cf2f72b2;p=soc.git

comment out wrflag as it should already be in the fu.wr.rel logic
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 95aed902..aa63d6d9 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -177,7 +177,7 @@ class NonProductionCore(Elaboratable):
 
                     # connect request-read to picker input, and output to go-wr
                     fu_active = fu_bitdict[funame]
-                    pick = fu.wr.rel[idx] & fu_active & wrflag
+                    pick = fu.wr.rel[idx] & fu_active #& wrflag
                     comb += wrpick.i[pi].eq(pick)
                     sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
                     # connect regfile port to input