From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 14 Apr 2018 05:47:14 +0000 (+0100)
Subject: add virtual reg illustration
X-Git-Tag: convert-csv-opcode-to-binary~5680
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=114e9940bee02e6d413fdea8b816a704fbb54454;p=libreriscv.git

add virtual reg illustration
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 9b80ffc92..6ca79263c 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1032,6 +1032,46 @@ translates effectively to:
   (caveat: anything not specified drops through to software-emulation / traps)
 * TODO
 
+# Register reordering <a name="register_reordering"></a>
+
+Register File 
+
+| Reg Num | Bits |
+| r0 | (32..0) |
+| r1 | (32..0) |
+| r2 | (32..0) |
+| r3 | (32..0) |
+| r4 | (32..0) |
+| r5 | (32..0) |
+| r6 | (32..0) |
+| r7 | (32..0) |
+
+Vectorised CSR
+
+| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
+
+Vector Length CSR
+
+| Reg Num | (3..0) |
+| r0 | 2 |
+| r1 | 0 |
+| r2 | 1 |
+| r3 | 1 |
+| r4 | 3 |
+| r5 | 0 |
+| r6 | 0 |
+| r7 | 1 |
+
+Virtual Register Reordering:
+
+| Reg Num | Bits (0) | Bits (1) | Bits (2) |
+| r0 | (32..0) | (32..0) |
+| r2 | (32..0) |
+| r3 | (32..0) |
+| r4 | (32..0) | (32..0) | (32..0) |
+| r7 | (32..0) |
+
 # Analysis of CSR decoding on latency <a name="csr_decoding_analysis"></a>
 
 It could indeed have been logically deduced (or expected), that there