From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jul 2019 11:43:38 +0000 (+0100)
Subject: remove "fail" in test
X-Git-Tag: ls180-24jan2020~894
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=115eebe2bb53bef0051e26e7be50fc8bc3e06f53;p=ieee754fpu.git

remove "fail" in test
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index 6a174ce2..3d58d0de 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -186,7 +186,6 @@ class TestDivPipeCore(unittest.TestCase):
             vl = rtlil.convert(dut, ports=[*dut.i, *dut.o])
             with open(f"{base_name}.il", "w") as f:
                 f.write(vl)
-        self.fail("generated invalid rtlil")  # FIXME: remove when fixed
         dut = DivPipeCoreTestPipeline(core_config)
         with Simulator(dut,
                        vcd_file=f"{base_name}.vcd",