From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 8 Jun 2012 16:06:12 +0000 (+0200)
Subject: Use super() instead of calling parent constructors directly
X-Git-Tag: 24jan2021_ls180~2099^2~934
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11674242c4c18da46df504ac85eaa3814c8b53b3;p=litex.git

Use super() instead of calling parent constructors directly
---

diff --git a/migen/actorlib/control.py b/migen/actorlib/control.py
index 004d4f8e..9163bcf5 100644
--- a/migen/actorlib/control.py
+++ b/migen/actorlib/control.py
@@ -20,7 +20,7 @@ class For(Actor):
 			for n, bv in enumerate(self.d_bv)]
 		l_source = [("d{0}".format(n), bv)
 			for n, bv in enumerate(self.d_bv)]
-		Actor.__init__(self,
+		super().__init__(
 			("sink", Sink, l_sink),
 			("source", Source, l_source))
 	
diff --git a/migen/bank/description.py b/migen/bank/description.py
index 01d59017..7f79ca6a 100644
--- a/migen/bank/description.py
+++ b/migen/bank/description.py
@@ -38,7 +38,7 @@ class RegisterFields:
 class RegisterField(RegisterFields):
 	def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
 		self.field = Field(name, size, access_bus, access_dev, reset)
-		RegisterFields.__init__(self, name, [self.field])
+		super().__init__(name, [self.field])
 
 class FieldAlias:
 	def __init__(self, f, start, end):
diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 9fff20a2..af6064da 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -10,7 +10,7 @@ _desc = Description(
 
 class Interface(SimpleInterface):
 	def __init__(self):
-		SimpleInterface.__init__(self, _desc)
+		super().__init__(_desc)
 
 class Interconnect(SimpleInterconnect):
 	pass
diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index 5365b795..35a8f8a1 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -20,11 +20,11 @@ _desc = Description(
 
 class Interface(SimpleInterface):
 	def __init__(self):
-		SimpleInterface.__init__(self, _desc)
+		super().__init__(_desc)
 
 class InterconnectPointToPoint(SimpleInterconnect):
 	def __init__(self, master, slave):
-		SimpleInterconnect.__init__(self, master, [slave])
+		super().__init__(master, [slave])
 
 class Arbiter:
 	def __init__(self, masters, target):
diff --git a/migen/flow/actor.py b/migen/flow/actor.py
index 04793606..7159c2a7 100644
--- a/migen/flow/actor.py
+++ b/migen/flow/actor.py
@@ -93,7 +93,7 @@ class SequentialActor(BinaryActor):
 	def __init__(self, delay, *endpoint_descriptions, **misc):
 		self.delay = delay
 		self.trigger = Signal()
-		BinaryActor.__init__(*endpoint_descriptions, **misc)
+		super().__init__(*endpoint_descriptions, **misc)
 
 	def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i):
 		ready = Signal()
@@ -125,7 +125,7 @@ class PipelinedActor(BinaryActor):
 	def __init__(self, latency, *endpoint_descriptions, **misc):
 		self.latency = latency
 		self.pipe_ce = Signal()
-		BinaryActor.__init__(*endpoint_descriptions, **misc)
+		super().__init__(*endpoint_descriptions, **misc)
 
 	def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i):
 		valid = Signal(BV(self.latency))
diff --git a/migen/flow/ala.py b/migen/flow/ala.py
index ca0da7e5..7e71c524 100644
--- a/migen/flow/ala.py
+++ b/migen/flow/ala.py
@@ -7,7 +7,7 @@ from migen.corelogic import divider
 class _SimpleBinary(CombinatorialActor):
 	def __init__(self, op, bv_op, bv_r):
 		self.op = op
-		CombinatorialActor.__init__(self,
+		super().__init____(
 			("operands", Sink, [("a", bv_op), ("b", bv_op)]),
 			("result", Source, [("r", bv_r)]))
 
@@ -19,48 +19,48 @@ class _SimpleBinary(CombinatorialActor):
 
 class Add(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "+", bv, BV(bv.width+1, bv.signed))
+		super().__init__("+", bv, BV(bv.width+1, bv.signed))
 
 class Sub(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "-", bv, BV(bv.width+1, bv.signed))
+		super().__init__("-", bv, BV(bv.width+1, bv.signed))
 
 class Mul(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "*", bv, BV(2*bv.width, bv.signed))
+		super().__init__("*", bv, BV(2*bv.width, bv.signed))
 
 class And(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "&", bv, bv)
+		super().__init__("&", bv, bv)
 
 class Xor(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "^", bv, bv)
+		super().__init__("^", bv, bv)
 
 class Or(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "|", bv, bv)
+		super().__init__("|", bv, bv)
 
 class LT(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "<", bv, BV(1))
+		super().__init__("<", bv, BV(1))
 
 class LE(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "<=", bv, BV(1))
+		super().__init__("<=", bv, BV(1))
 
 class EQ(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "==", bv, BV(1))
+		super().__init__("==", bv, BV(1))
 
 class NE(_SimpleBinary):
 	def __init__(self, bv):
-		_SimpleBinary.__init__(self, "!=", bv, BV(1))
+		super().__init__("!=", bv, BV(1))
 
 class DivMod(SequentialActor):
 	def __init__(self, width):
 		self.div = divider.Divider(width)
-		SequentialActor.__init__(self, width,
+		super().__init__(width,
 			("operands", Sink, [("dividend", self.div.dividend_i), ("divisor", self.div.divisor_i)]),
 			("result", Source, [("quotient", self.div.quotient_o), ("remainder", self.div.remainder_o)]))
 
diff --git a/migen/flow/network.py b/migen/flow/network.py
index fc9c7214..5eb98ac7 100644
--- a/migen/flow/network.py
+++ b/migen/flow/network.py
@@ -7,7 +7,7 @@ from migen.corelogic.misc import optree
 class CompositeActor(Actor):
 	def __init__(self, dfg): # TODO: endpoints
 		self.dfg = dfg
-		Actor.__init__(self)
+		super().__init__()
 	
 	def get_fragment(self):
 		this_fragments = [get_conn_fragment(x[0].endpoints[x[2]["source"]], x[1].endpoints[x[2]["sink"]])
diff --git a/migen/flow/plumbing.py b/migen/flow/plumbing.py
index 25921f18..017f037d 100644
--- a/migen/flow/plumbing.py
+++ b/migen/flow/plumbing.py
@@ -5,7 +5,7 @@ from migen.corelogic.misc import optree
 
 class Buffer(PipelinedActor):
 	def __init__(self, layout):
-		PipelinedActor.__init__(self, 1,
+		super().__init__(1,
 			("d", Sink, layout), ("q", Source, layout))
 	
 	def get_process_fragment(self):
@@ -22,7 +22,7 @@ class Combinator(CombinatorialActor):
 			for n, r in enumerate(subrecords)]
 		ep_source = ("source", Source, source)
 		eps.append(ep_source)
-		CombinatorialActor.__init__(self, *eps)
+		super().__init__(*eps)
 
 	def get_fragment(self):
 		source = self.endpoints["source"]
@@ -40,6 +40,6 @@ class Splitter(CombinatorialActor):
 			for n, r in enumerate(subrecords)]
 		ep_sink = ("sink", Sink, sink)
 		eps.append(ep_sink)
-		CombinatorialActor.__init__(self, *eps)
+		super().__init__(*eps)
 		
 	# TODO def get_fragment(self):