From: Jędrzej Boczar Date: Wed, 27 May 2020 13:13:16 +0000 (+0200) Subject: bios: move I2C from liblitedram to libbase X-Git-Tag: 24jan2021_ls180~276^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1172c10afb7955109890f844641c903d890d4ea6;p=litex.git bios: move I2C from liblitedram to libbase --- diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile index 0e288a43..4ab4a7d5 100755 --- a/litex/soc/software/bios/Makefile +++ b/litex/soc/software/bios/Makefile @@ -17,6 +17,7 @@ OBJECTS = isr.o \ cmd_bios.o \ cmd_mem.o \ cmd_boot.o \ + cmd_i2c.o \ cmd_spiflash.o \ cmd_litedram.o \ cmd_liteeth.o \ diff --git a/litex/soc/software/bios/cmds/cmd_i2c.c b/litex/soc/software/bios/cmds/cmd_i2c.c new file mode 100644 index 00000000..6c53b76c --- /dev/null +++ b/litex/soc/software/bios/cmds/cmd_i2c.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: BSD-Source-Code + +#include +#include +#include + +#include +#include + +#include "../command.h" +#include "../helpers.h" + + +/** + * Command "i2creset" + * + * Reset I2C line state in case a slave locks the line. + * + */ +#ifdef CSR_I2C_BASE +define_command(i2creset, i2c_reset, "Reset I2C line state", I2C_CMDS); +#endif + +/** + * Command "i2cwr" + * + * Write I2C slave memory using 7-bit slave address and 8-bit memory address. + * + */ +#ifdef CSR_I2C_BASE +static void i2cwr_handler(int nb_params, char **params) +{ + int i; + char *c; + unsigned char write_params[32]; // also indirectly limited by CMD_LINE_BUFFER_SIZE + + if (nb_params < 2) { + printf("i2cwr [, ...]"); + return; + } + + if (nb_params - 1 > sizeof(write_params)) { + printf("Max data length is %d", sizeof(write_params)); + return; + } + + for (i = 0; i < nb_params; ++i) { + write_params[i] = strtoul(params[i], &c, 0); + if (*c != 0) { + printf("Incorrect value of parameter %d", i); + return; + } + } + + if (!i2c_write(write_params[0], write_params[1], &write_params[2], nb_params - 2)) { + printf("Error during I2C write"); + return; + } +} +define_command(i2cwr, i2cwr_handler, "Write over I2C", I2C_CMDS); +#endif + +/** + * Command "i2crd" + * + * Read I2C slave memory using 7-bit slave address and 8-bit memory address. + * + */ +#ifdef CSR_I2C_BASE +static void i2crd_handler(int nb_params, char **params) +{ + char *c; + int len; + unsigned char slave_addr, addr; + unsigned char buf[256]; + bool send_stop = true; + + if (nb_params < 3) { + printf("i2crd []"); + return; + } + + slave_addr = strtoul(params[0], &c, 0); + if (*c != 0) { + printf("Incorrect slave address"); + return; + } + + addr = strtoul(params[1], &c, 0); + if (*c != 0) { + printf("Incorrect memory address"); + return; + } + + len = strtoul(params[2], &c, 0); + if (*c != 0) { + printf("Incorrect data length"); + return; + } + if (len > sizeof(buf)) { + printf("Max data count is %d", sizeof(buf)); + return; + } + + if (nb_params > 3) { + send_stop = strtoul(params[3], &c, 0) != 0; + if (*c != 0) { + printf("Incorrect send_stop value"); + return; + } + } + + if (!i2c_read(slave_addr, addr, buf, len, send_stop)) { + printf("Error during I2C read"); + return; + } + + dump_bytes((unsigned int *) buf, len, addr); +} +define_command(i2crd, i2crd_handler, "Read over I2C", I2C_CMDS); +#endif diff --git a/litex/soc/software/bios/cmds/cmd_litedram.c b/litex/soc/software/bios/cmds/cmd_litedram.c index 17d0bd17..026ab882 100644 --- a/litex/soc/software/bios/cmds/cmd_litedram.c +++ b/litex/soc/software/bios/cmds/cmd_litedram.c @@ -5,6 +5,7 @@ #include #include +#include #include "sdram.h" @@ -223,115 +224,6 @@ define_command(sdrlevel, sdrlevel, "Perform read/write leveling", LITEDRAM_CMDS) define_command(memtest, memtest, "Run a memory test", LITEDRAM_CMDS); #endif -/** - * Command "i2creset" - * - * Reset I2C line state in case a slave locks the line. - * - */ -#ifdef CSR_I2C_BASE -define_command(i2creset, i2c_reset, "Reset I2C line state", LITEDRAM_CMDS); -#endif - -/** - * Command "i2cwr" - * - * Write I2C slave memory using 7-bit slave address and 8-bit memory address. - * - */ -#ifdef CSR_I2C_BASE -static void i2cwr_handler(int nb_params, char **params) -{ - int i; - char *c; - unsigned char write_params[32]; // also indirectly limited by CMD_LINE_BUFFER_SIZE - - if (nb_params < 2) { - printf("i2cwr [, ...]"); - return; - } - - if (nb_params - 1 > sizeof(write_params)) { - printf("Max data length is %d", sizeof(write_params)); - return; - } - - for (i = 0; i < nb_params; ++i) { - write_params[i] = strtoul(params[i], &c, 0); - if (*c != 0) { - printf("Incorrect value of parameter %d", i); - return; - } - } - - if (!i2c_write(write_params[0], write_params[1], &write_params[2], nb_params - 2)) { - printf("Error during I2C write"); - return; - } -} -define_command(i2cwr, i2cwr_handler, "Write over I2C", LITEDRAM_CMDS); -#endif - -/** - * Command "i2crd" - * - * Read I2C slave memory using 7-bit slave address and 8-bit memory address. - * - */ -#ifdef CSR_I2C_BASE -static void i2crd_handler(int nb_params, char **params) -{ - char *c; - int len; - unsigned char slave_addr, addr; - unsigned char buf[256]; - bool send_stop = true; - - if (nb_params < 3) { - printf("i2crd []"); - return; - } - - slave_addr = strtoul(params[0], &c, 0); - if (*c != 0) { - printf("Incorrect slave address"); - return; - } - - addr = strtoul(params[1], &c, 0); - if (*c != 0) { - printf("Incorrect memory address"); - return; - } - - len = strtoul(params[2], &c, 0); - if (*c != 0) { - printf("Incorrect data length"); - return; - } - if (len > sizeof(buf)) { - printf("Max data count is %d", sizeof(buf)); - return; - } - - if (nb_params > 3) { - send_stop = strtoul(params[3], &c, 0) != 0; - if (*c != 0) { - printf("Incorrect send_stop value"); - return; - } - } - - if (!i2c_read(slave_addr, addr, buf, len, send_stop)) { - printf("Error during I2C read"); - return; - } - - dump_bytes((unsigned int *) buf, len, addr); -} -define_command(i2crd, i2crd_handler, "Read over I2C", LITEDRAM_CMDS); -#endif - /** * Command "spdread" * diff --git a/litex/soc/software/bios/command.h b/litex/soc/software/bios/command.h index 1640231f..05a93e80 100644 --- a/litex/soc/software/bios/command.h +++ b/litex/soc/software/bios/command.h @@ -15,6 +15,7 @@ #define MEM_CMDS 3 #define BOOT_CMDS 3 #define SPIFLASH_CMDS 4 +#define I2C_CMDS 4 #define LITEDRAM_CMDS 4 #define LITEETH_CMDS 5 #define LITESDCARD_CMDS 7 diff --git a/litex/soc/software/include/base/i2c.h b/litex/soc/software/include/base/i2c.h new file mode 100644 index 00000000..7021c942 --- /dev/null +++ b/litex/soc/software/include/base/i2c.h @@ -0,0 +1,26 @@ +#ifndef __I2C_H +#define __I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* I2C frequency defaults to a safe value in range 10-100 kHz to be compatible with SMBus */ +#ifndef I2C_FREQ_HZ +#define I2C_FREQ_HZ 50000 +#endif + +#define I2C_ADDR_WR(addr) ((addr) << 1) +#define I2C_ADDR_RD(addr) (((addr) << 1) | 1u) + +void i2c_reset(void); +bool i2c_write(unsigned char slave_addr, unsigned char addr, const unsigned char *data, unsigned int len); +bool i2c_read(unsigned char slave_addr, unsigned char addr, unsigned char *data, unsigned int len, bool send_stop); + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H */ diff --git a/litex/soc/software/libbase/Makefile b/litex/soc/software/libbase/Makefile index b29bffb4..dff9f718 100755 --- a/litex/soc/software/libbase/Makefile +++ b/litex/soc/software/libbase/Makefile @@ -1,8 +1,8 @@ include ../include/generated/variables.mak include $(SOC_DIRECTORY)/software/common.mak -OBJECTS=exception.o libc.o errno.o crc16.o crc32.o console.o \ - system.o id.o uart.o time.o qsort.o strtod.o spiflash.o strcasecmp.o +OBJECTS = exception.o libc.o errno.o crc16.o crc32.o console.o \ + system.o id.o uart.o time.o qsort.o strtod.o spiflash.o strcasecmp.o i2c.o all: crt0-ctr.o crt0-xip.o libbase.a libbase-nofloat.a diff --git a/litex/soc/software/libbase/i2c.c b/litex/soc/software/libbase/i2c.c new file mode 100644 index 00000000..cd15abb5 --- /dev/null +++ b/litex/soc/software/libbase/i2c.c @@ -0,0 +1,204 @@ +// This file is Copyright (c) 2020 Antmicro +#include +#include + +#ifdef CSR_I2C_BASE + +#define I2C_PERIOD_CYCLES (CONFIG_CLOCK_FREQUENCY / I2C_FREQ_HZ) +#define I2C_DELAY(n) cdelay((n)*I2C_PERIOD_CYCLES/4) + +static inline void cdelay(int i) +{ + while(i > 0) { + __asm__ volatile(CONFIG_CPU_NOP); + i--; + } +} + +static inline void i2c_oe_scl_sda(bool oe, bool scl, bool sda) +{ + i2c_w_write( + ((oe & 1) << CSR_I2C_W_OE_OFFSET) | + ((scl & 1) << CSR_I2C_W_SCL_OFFSET) | + ((sda & 1) << CSR_I2C_W_SDA_OFFSET) + ); +} + +// START condition: 1-to-0 transition of SDA when SCL is 1 +static void i2c_start(void) +{ + i2c_oe_scl_sda(1, 1, 1); + I2C_DELAY(1); + i2c_oe_scl_sda(1, 1, 0); + I2C_DELAY(1); + i2c_oe_scl_sda(1, 0, 0); + I2C_DELAY(1); +} + +// STOP condition: 0-to-1 transition of SDA when SCL is 1 +static void i2c_stop(void) +{ + i2c_oe_scl_sda(1, 0, 0); + I2C_DELAY(1); + i2c_oe_scl_sda(1, 1, 0); + I2C_DELAY(1); + i2c_oe_scl_sda(1, 1, 1); + I2C_DELAY(1); + i2c_oe_scl_sda(0, 1, 1); +} + +// Call when in the middle of SCL low, advances one clk period +static void i2c_transmit_bit(int value) +{ + i2c_oe_scl_sda(1, 0, value); + I2C_DELAY(1); + i2c_oe_scl_sda(1, 1, value); + I2C_DELAY(2); + i2c_oe_scl_sda(1, 0, value); + I2C_DELAY(1); + i2c_oe_scl_sda(0, 0, 0); // release line +} + +// Call when in the middle of SCL low, advances one clk period +static int i2c_receive_bit(void) +{ + int value; + i2c_oe_scl_sda(0, 0, 0); + I2C_DELAY(1); + i2c_oe_scl_sda(0, 1, 0); + I2C_DELAY(1); + // read in the middle of SCL high + value = i2c_r_read() & 1; + I2C_DELAY(1); + i2c_oe_scl_sda(0, 0, 0); + I2C_DELAY(1); + return value; +} + +// Send data byte and return 1 if slave sends ACK +static bool i2c_transmit_byte(unsigned char data) +{ + int i; + int ack; + + // SCL should have already been low for 1/4 cycle + i2c_oe_scl_sda(0, 0, 0); + for (i = 0; i < 8; ++i) { + // MSB first + i2c_transmit_bit((data & (1 << 7)) != 0); + data <<= 1; + } + ack = i2c_receive_bit(); + + // 0 from slave means ack + return ack == 0; +} + +// Read data byte and send ACK if ack=1 +static unsigned char i2c_receive_byte(bool ack) +{ + int i; + unsigned char data = 0; + + for (i = 0; i < 8; ++i) { + data <<= 1; + data |= i2c_receive_bit(); + } + i2c_transmit_bit(!ack); + + return data; +} + +// Reset line state +void i2c_reset(void) +{ + int i; + i2c_oe_scl_sda(1, 1, 1); + I2C_DELAY(8); + for (i = 0; i < 9; ++i) { + i2c_oe_scl_sda(1, 0, 1); + I2C_DELAY(2); + i2c_oe_scl_sda(1, 1, 1); + I2C_DELAY(2); + } + i2c_oe_scl_sda(0, 0, 1); + I2C_DELAY(1); + i2c_stop(); + i2c_oe_scl_sda(0, 1, 1); + I2C_DELAY(8); +} + +/* + * Read slave memory over I2C starting at given address + * + * First writes the memory starting address, then reads the data: + * START WR(slaveaddr) WR(addr) STOP START WR(slaveaddr) RD(data) RD(data) ... STOP + * Some chips require that after transmiting the address, there will be no STOP in between: + * START WR(slaveaddr) WR(addr) START WR(slaveaddr) RD(data) RD(data) ... STOP + */ +bool i2c_read(unsigned char slave_addr, unsigned char addr, unsigned char *data, unsigned int len, bool send_stop) +{ + int i; + + i2c_start(); + + if(!i2c_transmit_byte(I2C_ADDR_WR(slave_addr))) { + i2c_stop(); + return false; + } + if(!i2c_transmit_byte(addr)) { + i2c_stop(); + return false; + } + + if (send_stop) { + i2c_stop(); + } + i2c_start(); + + if(!i2c_transmit_byte(I2C_ADDR_RD(slave_addr))) { + i2c_stop(); + return false; + } + for (i = 0; i < len; ++i) { + data[i] = i2c_receive_byte(i != len - 1); + } + + i2c_stop(); + + return true; +} + +/* + * Write slave memory over I2C starting at given address + * + * First writes the memory starting address, then writes the data: + * START WR(slaveaddr) WR(addr) WR(data) WR(data) ... STOP + */ +bool i2c_write(unsigned char slave_addr, unsigned char addr, const unsigned char *data, unsigned int len) +{ + int i; + + i2c_start(); + + if(!i2c_transmit_byte(I2C_ADDR_WR(slave_addr))) { + i2c_stop(); + return false; + } + if(!i2c_transmit_byte(addr)) { + i2c_stop(); + return false; + } + for (i = 0; i < len; ++i) { + if(!i2c_transmit_byte(data[i])) { + i2c_stop(); + return false; + } + } + + i2c_stop(); + + return true; +} + +#endif /* CSR_I2C_BASE */ diff --git a/litex/soc/software/liblitedram/Makefile b/litex/soc/software/liblitedram/Makefile index c6113c0a..c541e3f6 100644 --- a/litex/soc/software/liblitedram/Makefile +++ b/litex/soc/software/liblitedram/Makefile @@ -1,7 +1,7 @@ include ../include/generated/variables.mak include $(SOC_DIRECTORY)/software/common.mak -OBJECTS = sdram.o i2c.o +OBJECTS = sdram.o all: liblitedram.a diff --git a/litex/soc/software/liblitedram/i2c.c b/litex/soc/software/liblitedram/i2c.c deleted file mode 100644 index af40b8f4..00000000 --- a/litex/soc/software/liblitedram/i2c.c +++ /dev/null @@ -1,205 +0,0 @@ -// This file is Copyright (c) 2020 Antmicro - -#include -#include "i2c.h" - -#ifdef CSR_I2C_BASE - -#define I2C_PERIOD_CYCLES (CONFIG_CLOCK_FREQUENCY / I2C_FREQ_HZ) -#define I2C_DELAY(n) cdelay((n)*I2C_PERIOD_CYCLES/4) - -static inline void cdelay(int i) -{ - while(i > 0) { - __asm__ volatile(CONFIG_CPU_NOP); - i--; - } -} - -static inline void i2c_oe_scl_sda(bool oe, bool scl, bool sda) -{ - i2c_w_write( - ((oe & 1) << CSR_I2C_W_OE_OFFSET) | - ((scl & 1) << CSR_I2C_W_SCL_OFFSET) | - ((sda & 1) << CSR_I2C_W_SDA_OFFSET) - ); -} - -// START condition: 1-to-0 transition of SDA when SCL is 1 -static void i2c_start(void) -{ - i2c_oe_scl_sda(1, 1, 1); - I2C_DELAY(1); - i2c_oe_scl_sda(1, 1, 0); - I2C_DELAY(1); - i2c_oe_scl_sda(1, 0, 0); - I2C_DELAY(1); -} - -// STOP condition: 0-to-1 transition of SDA when SCL is 1 -static void i2c_stop(void) -{ - i2c_oe_scl_sda(1, 0, 0); - I2C_DELAY(1); - i2c_oe_scl_sda(1, 1, 0); - I2C_DELAY(1); - i2c_oe_scl_sda(1, 1, 1); - I2C_DELAY(1); - i2c_oe_scl_sda(0, 1, 1); -} - -// Call when in the middle of SCL low, advances one clk period -static void i2c_transmit_bit(int value) -{ - i2c_oe_scl_sda(1, 0, value); - I2C_DELAY(1); - i2c_oe_scl_sda(1, 1, value); - I2C_DELAY(2); - i2c_oe_scl_sda(1, 0, value); - I2C_DELAY(1); - i2c_oe_scl_sda(0, 0, 0); // release line -} - -// Call when in the middle of SCL low, advances one clk period -static int i2c_receive_bit(void) -{ - int value; - i2c_oe_scl_sda(0, 0, 0); - I2C_DELAY(1); - i2c_oe_scl_sda(0, 1, 0); - I2C_DELAY(1); - // read in the middle of SCL high - value = i2c_r_read() & 1; - I2C_DELAY(1); - i2c_oe_scl_sda(0, 0, 0); - I2C_DELAY(1); - return value; -} - -// Send data byte and return 1 if slave sends ACK -static bool i2c_transmit_byte(unsigned char data) -{ - int i; - int ack; - - // SCL should have already been low for 1/4 cycle - i2c_oe_scl_sda(0, 0, 0); - for (i = 0; i < 8; ++i) { - // MSB first - i2c_transmit_bit((data & (1 << 7)) != 0); - data <<= 1; - } - ack = i2c_receive_bit(); - - // 0 from slave means ack - return ack == 0; -} - -// Read data byte and send ACK if ack=1 -static unsigned char i2c_receive_byte(bool ack) -{ - int i; - unsigned char data = 0; - - for (i = 0; i < 8; ++i) { - data <<= 1; - data |= i2c_receive_bit(); - } - i2c_transmit_bit(!ack); - - return data; -} - -// Reset line state -void i2c_reset(void) -{ - int i; - i2c_oe_scl_sda(1, 1, 1); - I2C_DELAY(8); - for (i = 0; i < 9; ++i) { - i2c_oe_scl_sda(1, 0, 1); - I2C_DELAY(2); - i2c_oe_scl_sda(1, 1, 1); - I2C_DELAY(2); - } - i2c_oe_scl_sda(0, 0, 1); - I2C_DELAY(1); - i2c_stop(); - i2c_oe_scl_sda(0, 1, 1); - I2C_DELAY(8); -} - -/* - * Read slave memory over I2C starting at given address - * - * First writes the memory starting address, then reads the data: - * START WR(slaveaddr) WR(addr) STOP START WR(slaveaddr) RD(data) RD(data) ... STOP - * Some chips require that after transmiting the address, there will be no STOP in between: - * START WR(slaveaddr) WR(addr) START WR(slaveaddr) RD(data) RD(data) ... STOP - */ -bool i2c_read(unsigned char slave_addr, unsigned char addr, unsigned char *data, unsigned int len, bool send_stop) -{ - int i; - - i2c_start(); - - if(!i2c_transmit_byte(I2C_ADDR_WR(slave_addr))) { - i2c_stop(); - return false; - } - if(!i2c_transmit_byte(addr)) { - i2c_stop(); - return false; - } - - if (send_stop) { - i2c_stop(); - } - i2c_start(); - - if(!i2c_transmit_byte(I2C_ADDR_RD(slave_addr))) { - i2c_stop(); - return false; - } - for (i = 0; i < len; ++i) { - data[i] = i2c_receive_byte(i != len - 1); - } - - i2c_stop(); - - return true; -} - -/* - * Write slave memory over I2C starting at given address - * - * First writes the memory starting address, then writes the data: - * START WR(slaveaddr) WR(addr) WR(data) WR(data) ... STOP - */ -bool i2c_write(unsigned char slave_addr, unsigned char addr, const unsigned char *data, unsigned int len) -{ - int i; - - i2c_start(); - - if(!i2c_transmit_byte(I2C_ADDR_WR(slave_addr))) { - i2c_stop(); - return false; - } - if(!i2c_transmit_byte(addr)) { - i2c_stop(); - return false; - } - for (i = 0; i < len; ++i) { - if(!i2c_transmit_byte(data[i])) { - i2c_stop(); - return false; - } - } - - i2c_stop(); - - return true; -} - -#endif /* CSR_I2C_BASE */ diff --git a/litex/soc/software/liblitedram/i2c.h b/litex/soc/software/liblitedram/i2c.h deleted file mode 100644 index c0cc2bfe..00000000 --- a/litex/soc/software/liblitedram/i2c.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __I2C_H -#define __I2C_H - -#include -#include - -/* I2C frequency defaults to a safe value in range 10-100 kHz to be compatible with SMBus */ -#ifndef I2C_FREQ_HZ -#define I2C_FREQ_HZ 50000 -#endif - -#define I2C_ADDR_WR(addr) ((addr) << 1) -#define I2C_ADDR_RD(addr) (((addr) << 1) | 1u) - -void i2c_reset(void); -bool i2c_write(unsigned char slave_addr, unsigned char addr, const unsigned char *data, unsigned int len); -bool i2c_read(unsigned char slave_addr, unsigned char addr, unsigned char *data, unsigned int len, bool send_stop); - -#endif /* __I2C_H */ diff --git a/litex/soc/software/liblitedram/sdram.h b/litex/soc/software/liblitedram/sdram.h index 7deb82e3..21433c03 100644 --- a/litex/soc/software/liblitedram/sdram.h +++ b/litex/soc/software/liblitedram/sdram.h @@ -2,7 +2,6 @@ #define __SDRAM_H #include -#include "i2c.h" void sdrsw(void); void sdrhw(void);