From: lkcl <lkcl@web>
Date: Fri, 3 Jun 2022 13:58:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2000
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=117c02ac9ef26695ab2917e417eff660c99c652a;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 984347082..5ff58ff39 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -45,7 +45,8 @@ v3.0 32-bit instruction as a completely
 different encoding if SVP64-prefixed. It did not go well.
 The complexity that resulted
 in the decode phase was too great. The lesson was learned, the
-hard way: it is infinitely preferable to add a 32-bit Scalar Load-with-Shift
+hard way: it would be infinitely preferable
+to add a 32-bit Scalar Load-with-Shift
 instruction *first*, which then inherently becomes Vectorised.
 Perhaps a future Power ISA spec will have this Load-with-Shift instruction:
 both ARM and x86 have it, because it saves greatly on instruction count in