From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Sep 2018 01:45:26 +0000 (+0100)
Subject: add sv_insn_t class (inherits from insn_t)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11b47024904875cb559e7f8436d2809d566c1e7c;p=riscv-isa-sim.git

add sv_insn_t class (inherits from insn_t)
---

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
new file mode 100644
index 0000000..0508de1
--- /dev/null
+++ b/riscv/sv_decode.h
@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+#ifndef _RISCV_SV_DECODE_H
+#define _RISCV_SV_DECODE_H
+
+#include "sv.h"
+#include "decode.h"
+
+class sv_insn_t: public insn_t
+{
+public:
+  uint64_t rd () { return remap(insn_t::rd()); }
+  uint64_t rs1() { return remap(insn_t::rs1(); }
+  uint64_t rs2() { return remap(insn_t::rs2(); }
+  uint64_t rs3() { return remap(insn_t::rs3(); }
+private:
+  // remaps the register through the lookup table.
+  // will need to take the current loop index/offset somehow
+  uint64_t remap(uint64_t reg) { return reg; } // TODO
+};
+
+#endif