From: Yehowshua <Yehowshua@web>
Date: Sat, 2 May 2020 06:10:43 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2774
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11bb83a7da71511ebea14c1c604301f08310555c;p=libreriscv.git

---

diff --git a/index.mdwn b/index.mdwn
index c4a544f4e..131955ecf 100644
--- a/index.mdwn
+++ b/index.mdwn
@@ -80,8 +80,24 @@ list](http://bugs.libre-riscv.org) and see if there are any bugs that
 pique your interest.
 3. After that, go ahead and take a look at the
    [git repositories](https://git.libre-riscv.org).
-Try and clone a repository with
-``git clone https://git.libre-riscv.org/git/repositoryname.git``
+
+    pip3 install virtualenv requests
+    mkdir ~/.virtualenvs && cd ~/.virtualenvs
+    python3 -m venv libresoc
+    source ~/.virtualenvs/bin/activate
+    
+    cd ~; mkdir libresoc; cd libresoc
+    git clone https://git.libre-riscv.org/git/nmutil.git
+    git clone https://git.libre-riscv.org/git/ieee754fpu.git
+    git clone https://git.libre-riscv.org/git/soc.git
+    
+    cd nmutil; pip3 install -e .; cd ..
+    cd ieee754fpu; pip3 install -e .; cd ..
+    cd soc; pip3 install -e .; cd ..
+    
+    python3 soc/src/soc/decoder/power_decoder.py
+
+
 4. If you plan to do HDL work, you should familiarize yourself with our
    [[HDL_workflow]].
 5. We do have funding available (see [[nlnet]]) upon completion of issues -