From: Eddie Hung Date: Sat, 28 Sep 2019 00:00:19 +0000 (-0700) Subject: Fix typo X-Git-Tag: working-ls180~881^2^2~211 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=11cb5fab004c005c6d674494b1486ee501037c5c;p=yosys.git Fix typo --- diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1d380135b..f42f5430f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1528,7 +1528,7 @@ std::vector RTLIL::Module::selected_wires() const std::vector RTLIL::Module::selected_cells() const { std::vector result; - result.reserve(wires_.size()); + result.reserve(cells_.size()); for (auto &it : cells_) if (design->selected(this, it.second)) result.push_back(it.second);